Processor with programmable configuration of logical-to-physical address translation on a per-client basis
AssigneeAgere Systems Inc.
InventorDavid A. Brown
Life of this patent
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Abstract
A network processor or other type of processor includes translation configuration circuitry which allows programmable configuration of logical-to-physical address translation on a per-client basis for multiple clients of the processor. In one aspect of the invention, the processor stores translation configuration information for a client. A read or write request from the client includes a logical address. The logical address is processed utilizing the stored translation configuration information for the client to generate a physical address. The physical address is utilized to access an internal or external memory.
Claims21
A processor comprising:
- a plurality of clients;
- translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
- address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client;
- and
- memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address;
- wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
A processing system comprising:
- a processor;
- and
- an external memory operatively coupled to the processor;
- the processor further comprising:
- a plurality of clients;
- translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
- address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client;
- and
- memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address;
- wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
A method for use in processing packets in a processor, the processor comprising a plurality of clients, the method comprising the steps of:
- storing translation configuration information for the plurality of clients of the processor in a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
- utilizing the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client;
- and
- accessing a memory utilizing the received physical address;
- wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
Dependencies are inferred from the claim text.