De-interleaving mechanism involving a multi-banked LLR buffer

A method comprising:

• (a) generating a plurality of De-interleaved Reorder Physical (DRP) addresses, wherein the plurality of DRP addresses comprises a plurality of sets of DRP addresses;
• (b) using each set of DRP addresses to simultaneously write a corresponding set of (Log-Likelihood Ratio) LLR values into a memory;
• and
• (c) reading the plurality of LLR values out of the memory in a de-interleaved order,
• wherein the DRP addresses are Pruned Bit Reversal Interleaved (PBRI) addresses, and wherein the memory is a multi-banked memory.

An apparatus comprising:

• a de-interleaver circuit that generates a plurality of De-interleaved Reorder Physical (DRP) addresses;
• and
• a multi-banked memory that uses the plurality of DRP addresses to simultaneously write a plurality of LLR values into the multi-banked memory such that no more than one LLR value is written into each bank of the multi-banked memory at a time,
• wherein the DRP addresses are Pruned Bit Reversal Interleaved (PBRI) addresses.

An apparatus, comprising:

• a multi-banked memory comprising a plurality of banks;
• and
• means for using a plurality of De-interleaved Reorder Physical (DRP) addresses for writing a plurality of sets of Log Likelihood Ratio (LLR) values into the multi-banked memory, wherein the LLR values of each set are simultaneously written into the multi-banked memory such that no more than one LLR value is written into each bank of the multi-banked memory at a time,
• wherein the DRP addresses are Pruned Bit Reversal Interleaved (PBRI) addresses.

A computer program product, comprising:

• a non-transitory computer-readable medium comprising:
• code for causing a computer to control a de-interleaver such that the de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses, and such that the DRP addresses are used to simultaneously write a corresponding plurality of (Log-Likelihood Ratio) LLR values into a multi-banked memory, wherein the multi-banked memory comprises a plurality of banks, and wherein no more than one LLR value is written into each bank of the multi-banked memory at a time;
• and
• code for causing the computer to control a decoder such that the decoder reads the plurality of LLR values out of the multi-banked memory in a de-interleaved order,
• wherein the DRP addresses are Pruned Bit Reversal Interleaved (PBRI) addresses.

A method comprising:

• (a) clearing a plurality Log-Likelihood Ratio (LLR) values from a word-location in a memory by performing a single write operation,
• wherein the word-location is one of a plurality of word-locations, and wherein all of the word-locations of the plurality of word-locations are cleared simultaneously,
• wherein the memory is a multi-banked memory, and wherein each of the word-locations of the plurality of word-locations is a part of a different bank of the multi-banked memory, and
• wherein an LLR value of a first sub-packet and an LLR value of a second sub-packet are both stored in the same bank of the multi-banked memory.

A method comprising:

• (a) clearing a plurality Log-Likelihood Ratio (LLR) values from a word-location in a memory by performing a single write operation;
• (b) interpreting an instruction;
• and
• (c) in response to the interpreting of (b) performing step (a) multiple times such that a plurality of word-locations identified by the instruction is cleared.