# US 8,572,320 B1 · Memory devices and systems including cache devices for memory modules

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- Number: US 8,572,320 B1
- Document ID: US8572320B1
- Status: Granted
- Kind: B1
- Application number: 12/577,695
- Filed: 2009-10-12
- Granted: 2013-10-29
- Earliest claimed: 2009-01-23
- Assignees: Cypress Semiconductor Corporation
- Applicants: Dinesh Maheshwari
- Inventors: Dinesh Maheshwari
- Web page: https://patentgrep.com/patent/US8572320B1

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 12/0862: with prefetch
- G06F 13/1673: {using buffers}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks}
- G06F 13/1684: {using multiple buses}
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory apparatus may include one or more cache memory integrated circuit (ICs), each of which may have compare circuitry that compares a received address with stored compare values, a cache memory that provides cached data in response to the compare circuitry, a controller interface having at least address and control signal input terminals, and a module output connection having at least address and control signal output terminals corresponding to the address and control signal input terminals.

## Claims

### Claim 1

A memory apparatus, comprising:
at least one cache memory integrated circuit (IC) comprising compare circuitry that compares a received address with stored compare values, the compare circuitry providing a configurable granularity in cache compare tries responsive to a configurable SET value;
cache memory that provides cached data in response to the compare circuitry, a controller interface having at least address and control signal input terminals, and
a module output connection having at least address and control signal output terminals corresponding to the address and control signal input terminals.

### Claim 2 (depends on 1)

The memory apparatus of claim 1, wherein:
the controller interface further includes interface data signal terminals, and
the module output connection includes connection data signal terminals corresponding to the interface data signal terminals.

### Claim 3 (depends on 2)

The memory apparatus of claim 2, wherein:
the at least one cache memory IC comprises a look-aside cache memory IC; and
the controller interface further includes a bus isolation circuit having at least a first data isolation circuit that selectively isolates or connects the interface data signal terminals to the connection data signal terminals.

### Claim 4 (depends on 1)

The memory apparatus of claim 1, wherein:
the at least one cache memory IC comprises a look through cache memory IC that further includes a memory apparatus interface coupled to the module output connection that generates memory control signals for at least one memory IC.

### Claim 5 (depends on 1)

The memory apparatus of claim 1, further including:
a plurality of module memory ICs coupled to at least the module output connections, wherein the at least one cache memory IC is configured to cache data for the module memory ICs, output cached data in response to a cache hit, and output stored data from the module memory ICs in response to a cache miss, and wherein the module memory ICs and the at least one cache memory IC are physically attached to a same circuit board.

### Claim 6

A method, comprising:
including at least one cache memory integrated circuit (IC) between at least input connections of a memory module circuit board and memory control signal paths for a plurality of memory ICs formed on the memory module circuit board, and
in response to a cache miss on the cache memory IC, placing non-accessed memory circuits on the cache memory IC into a low power consuming state and returning said non-accessed memory circuits to a higher power consuming state before a next command to the cache memory IC is expected, and
in response to predetermined address values on the at least input connections, generating memory standby commands on the memory control signal paths for placing memory ICs into a lower power consuming state from a higher power consuming state.

### Claim 7 (depends on 6)

The method of claim 6, wherein:
storing selected data received on the memory control signal paths in the cache memory (IC) as cached data; and
in response to read commands, outputting the cached data from the cache memory IC in lieu of outputting data from the memory control signal paths.

### Claim 8 (depends on 6)

The method of claim 6, further including:
upon receiving a cache read hit for data cached in the cache memory IC corresponding to a first address location, generating pre fetch read commands for a second address location on the memory control signal paths, the second address location being selected from: a location on a same module circuit board as the cache memory IC, or a location on a different module circuit board than the cache memory IC.

### Claim 9 (depends on 6)

The method of claim 6, further including:
upon receiving a cache read miss, enabling an output read data path through the cache memory IC to memory module data outputs,
caching first data on the enabled read data path in the cache memory IC, and
generating pre-fetch read commands for a predetermined address location on the memory control signal paths, the predetermined address corresponding to second data different from the first data, the second data being stored at a location selected from: a same module circuit board as the cache memory IC, or a different module circuit board than the cache memory IC; and
caching second data in the cache memory.

### Claim 10 (depends on 6)

The method of claim 6, further including:
in response to a cache hit, outputting a predetermined cache hit indication signal on at least one output connection of the memory module.

### Claim 11 (depends on 6)

The method of claim 6, wherein:
including at least one cache memory IC further includes including a plurality of cache memory ICs striped across a memory control data path, each cache memory IC being coupled to a different portion of the memory control data path.

### Claim 12 (depends on 6)

The method of claim 6, wherein:
including at least one cache memory IC further includes including a plurality of cache memory ICs, each cache memory IC storing tag data for at least one other cache memory IC, the tag of a cache memory IC indicating which data are cached in the cache memory IC.

### Claim 13 (depends on 6)

The method of claim 6, further including:
in response to predetermined address values on the at least input connections, generating memory activate commands on the memory control signal paths for placing memory ICs into a faster response state from a slower response state.

### Claim 14

A memory apparatus, comprising:
at least one cache memory integrated circuit (IC) including at least one cache memory array that stores cached data, cache compare circuitry that generates a cache hit indication in response to address data received at module input connections, the cache compare circuitry comprising a configurable granularity in cache compare tries responsive to a configurable SET value; and
a cache controller circuit, coupled to memory control output connections, that generates at least one memory device control signal compatible with predetermined memory ICs.

### Claim 15 (depends on 14)

The memory apparatus of claim 14, wherein:
the at least one memory device control signal comprises a clock enable signal (CKE) compatible with predetermined dynamic random access memory devices or nonvolatile memory devices.

### Claim 16 (depends on 14)

The memory apparatus of claim 14, further including:
an in-line memory module (IMM) circuit board; and
the cache memory device being coupled between signal connections of the IMM circuit board, and module signal lines formed on the IMM circuit board.

### Claim 17 (depends on 14)

The memory apparatus of claim 14, further including:
the cache controller circuit includes a cache hit indication circuit that generates predetermined cache hit indication that is output to a memory controller.

### Claim 18 (depends on 17)

The memory apparatus of claim 17, wherein:
the cache hit indication comprises data timing signals.

### Claim 19 (depends on 17)

The memory apparatus of claim 17, further including:
the cache hit indication signals include a transaction identification value received from a memory controller that identifies a memory controller transaction that results in a cache hit.