# US 8,572,313 B2 · Methods and apparatus providing high-speed content addressable memory (CAM) search-invalidates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,313 B2 - Document ID: US8572313B2 - Status: Granted - Kind: B2 - Application number: 13/269,701 - Filed: 2011-10-10 - Published: 2013-04-11 - Granted: 2013-10-29 - Earliest claimed: 2011-10-10 - Assignees: QUALCOMM Incorporated - Applicants: Manju Rathna Varma; David Paul Hoff; Jason Philip Martzloff - Inventors: Manju Rathna Varma; David Paul Hoff; Jason Philip Martzloff - Web page: https://patentgrep.com/patent/US8572313B2 ## CPC - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G11C 15/04: using semiconductor elements - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation. ## Claims ### Claim 1 A Content Addressable Memory (CAM) comprising: a CAM cell array configured to generate a match indicator, the CAM cell array comprising a plurality of CAM cells and a valid bit cell; and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search-invalidate operation. ### Claim 2 (depends on 1) The CAM of claim 1, wherein the blocking circuitry is configured to block the output of the valid bit cell from altering the match indicator from a start of the invalidate process to an end of the search-invalidate operation. ### Claim 3 (depends on 1) The CAM of claim 1, wherein the invalidate process is controlled by a self-timed clock signal. ### Claim 4 (depends on 1) The CAM of claim 1, wherein the search-invalidate operation is performed during one pulse of a system clock signal, and the invalidate process is performed during a pulse of a phase-based clock signal. ### Claim 5 (depends on 4) The CAM of claim 4 wherein the phase-based clock signal has a starting edge offset from a starting edge of the pulse of the system clock signal and an ending edge aligned with an ending edge of the pulse of the system clock signal. ### Claim 6 (depends on 4) The CAM of claim 4, wherein the blocking circuitry is configured to block the output of the valid bit cell from altering the match indicator during a time period from a starting edge of the phase-based clock signal to an ending edge of the phase-based clock signal. ### Claim 7 (depends on 1) The CAM of claim 1, wherein the CAM cell array further comprises invalidation circuitry configured to: determine that the match indicator is indicative of a match between an input data word and a valid data word stored by the CAM cell array; and write a bit value to the valid bit cell that indicates an invalid state in response to determining that the match indicator is indicative of a match between the input data word and the valid data word stored by the CAM cell array to thereby perform the invalidate process. ### Claim 8 (depends on 7) The CAM of claim 7, wherein the blocking circuitry is configured to block the output of the valid bit cell from altering the match indicator while the invalidation circuitry writes the bit value to the valid bit cell that indicates the invalid state. ### Claim 9 (depends on 8) The CAM of claim 8, wherein the blocking circuitry is further configured to continue to block the output of the valid bit cell from altering the match indicator until the search-invalidate operation is complete. ### Claim 10 (depends on 8) The CAM of claim 8, wherein by blocking the output of the valid bit cell, the blocking circuitry blocks a feedback path by which the match indicator would be altered in response to writing the bit value to the valid bit cell that indicates the invalid state. ### Claim 11 (depends on 1) The CAM of claim 1, wherein the blocking circuitry is configured to block only the output of the valid bit cell from altering the match indicator during the invalidate process of the search-invalidate operation. ### Claim 12 (depends on 1) The CAM of claim 1, wherein the blocking circuitry comprises an OR gate having a first input coupled to the output of the valid bit cell and a second input configured to receive an invalidate signal that is asserted during the invalidate process of the search-invalidate operation. ### Claim 13 (depends on 12) The CAM of claim 12, wherein the CAM cell array further comprises circuitry configured to assert the invalidate signal during the invalidate process of the search-invalidate operation if the match indicator indicates a match for the CAM cell array for a compare process of the search-invalidate operation. ### Claim 14 (depends on 1) The CAM of claim 1, wherein the blocking circuitry comprises a NOR gate having a first input coupled to the output of the valid bit cell and a second input configured to receive an invalidate signal that is asserted during the invalidate process of the search-invalidate operation. ### Claim 15 (depends on 14) The CAM of claim 14, wherein the CAM cell array further comprises circuitry configured to assert the invalidate signal during the invalidate process of the search-invalidate operation if the match indicator indicates a match for the CAM cell array for a compare process of the search-invalidate operation. ### Claim 16 (depends on 1) The CAM of claim 1 integrated in at least one semiconductor die. ### Claim 17 (depends on 1) The CAM of claim 1, further comprising a device selected from a group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which the CAM is integrated. ### Claim 18 A method of operation of a Content Addressable Memory (CAM) that comprises a CAM cell array including a plurality of CAM cells and a valid bit cell, comprising: during a comparison phase of a search-invalidate operation, generating a match indicator that is indicative of a match for the CAM cell array in response to a digital word stored by the plurality of CAM cells in the CAM cell array matching an input digital word and a bit stored by the valid bit cell being representative of a valid state; and during an invalidate phase of the search-invalidate operation, blocking an output of the valid bit cell from altering the match indicator while writing a bit representative of an invalid state to the valid bit cell. ### Claim 19 (depends on 18) The method of claim 18 wherein the match indicator is a high voltage level on a match line associated with the CAM cell array, and blocking the output of the valid bit cell from altering the match indicator while writing the bit representative of the invalid state to the valid bit cell comprises blocking the output of the valid bit cell from discharging the match indicator while writing the bit representative of the invalid state to the valid bit cell. ### Claim 20 (depends on 18) The method of claim 18 wherein the search-invalidate operation is performed during one pulse of a system clock signal, and blocking the output of the valid bit cell from altering the match indicator while writing the bit representative of the invalid state to the valid bit cell comprises blocking the output of the valid bit cell from altering the match indicator from a starting edge to an ending edge of a pulse of a phase-based clock signal. ### Claim 21 (depends on 20) The method of claim 20 wherein the phase-based clock signal has a starting edge offset from a starting edge of the pulse of the system clock signal and an ending edge aligned with an ending edge of the pulse of the system clock signal. ### Claim 22 A non-transitory computer-readable medium storing software for instructing a processor to: effect a search-invalidate operation for a Content Addressable Memory (CAM) that comprises a CAM cell array including a plurality of CAM cells and a valid bit cell by causing the CAM cell array to: during a comparison phase of the search-invalidate operation, generate a match indicator that is indicative of a match for the CAM cell array in response to a digital word stored by the plurality of CAM cells in the CAM cell array matching an input digital word and a bit stored by the valid bit cell being representative of a valid state; and during an invalidate phase of the search-invalidate operation, block an output of the valid bit cell from altering the match indicator while writing a bit representative of an invalid state to the valid bit cell. ### Claim 23 A Content Addressable Memory (CAM) comprising: a means for generating a match indicator, the means for generating comprising a plurality of CAM cells and a valid bit cell; and means for blocking an output of the valid bit cell from altering the match indicator during an invalidate process of a search-invalidate operation.