# US 8,572,308 B2 · Supporting variable sector sizes in flash storage devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,308 B2 - Document ID: US8572308B2 - Status: Granted - Kind: B2 - Application number: 12/492,103 - Filed: 2009-06-25 - Published: 2010-02-18 - Granted: 2013-10-29 - Earliest claimed: 2008-06-25 - Assignees: STEC, Inc. - Applicants: Mark Moshayedi; William Calvert; Stephen Russell Boorman; Simon Mark Haynes - Inventors: Mark Moshayedi; William Calvert; Stephen Russell Boorman; Simon Mark Haynes - Web page: https://patentgrep.com/patent/US8572308B2 ## CPC - G06F 3/0613: {in relation to throughput} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 11/1441: {Resetting or repowering} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A flash storage device comprises a plurality of data blocks, each data block comprising a plurality of data segments, a system memory, and a controller. The controller is configured to cache in the system memory a plurality of data sectors to be written, to write to a first one of the plurality of data segments a first one of the plurality of data sectors, to write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors, and to write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors. ## Claims ### Claim 1 A flash storage device, comprising: a plurality of data blocks, each data block comprising a plurality of data segments; a system memory, and a controller configured to: cache in the system memory a plurality of data sectors to be written; write to a first one of the plurality of data segments a first one of the plurality of data sectors; write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors; and write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors. ### Claim 2 (depends on 1) The flash storage device according to claim 1, wherein the controller is further configured to: calculate error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first one of the plurality of data segments; calculate error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second one of the plurality of data segments; and write the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second one of the plurality of data segments. ### Claim 3 (depends on 1) The flash storage device according to claim 1, wherein the first and second ones of the plurality of data segments are data segments of a same one of the plurality of data blocks. ### Claim 4 (depends on 1) The flash storage device according to claim 1, wherein the first and second ones of the plurality of data segments are adjacent data segments. ### Claim 5 (depends on 1) The flash storage device according to claim 1, wherein the plurality of data sectors to be written each have a same size of 2n bits, where n is a positive integer. ### Claim 6 (depends on 1) The flash storage device according to claim 1, wherein the plurality of data sectors to be written each have a same size of other than 2n bits, where n is a positive integer. ### Claim 7 (depends on 1) The flash storage device according to claim 1, wherein the system memory includes an addressing table correlating, for each of the plurality of data sectors, a logical address thereof with a physical location thereof in the corresponding one of the plurality of data blocks. ### Claim 8 (depends on 7) The flash storage device according to claim 7, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks. ### Claim 9 (depends on 1) The flash storage device according to claim 1, wherein the system memory comprises a random access memory in the controller. ### Claim 10 (depends on 1) The flash storage device according to claim 1, wherein the system memory comprises one or more buffers provided on one or more flash memory chips in which the plurality of data blocks are disposed. ### Claim 11 A method of writing data to a flash storage device comprising a plurality of data blocks, each data block comprising a plurality of data segments, the method comprising the steps of: caching in a system memory a plurality of data sectors to be written; writing a first one of the plurality of data sectors to a first data segment; writing a first portion of a second one of the plurality of data sectors to the first data segment; and writing a second portion of the second one of the plurality of data sectors to a second data segment. ### Claim 12 (depends on 11) The method according to claim 11, further comprising the steps of: calculating error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first data segment; calculating error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second data segment; and writing the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second data segment. ### Claim 13 (depends on 11) The method according to claim 11, wherein the first and second ones of the plurality of data segments are data segments of a same data block. ### Claim 14 (depends on 11) The method according to claim 11, wherein the first and second ones of the plurality of data segments are adjacent data segments. ### Claim 15 (depends on 11) The method according to claim 11, wherein the plurality of data sectors to be written each have a same size of 2n bits, where n is a positive integer. ### Claim 16 (depends on 11) The method according to claim 11, wherein the plurality of data sectors to be written each have a same size of other than 2n bits, where n is a positive integer. ### Claim 17 (depends on 11) The method according to claim 11, further comprising the step of: updating an addressing table correlating, for each of the first and second data sectors, a logical address thereof with a physical location thereof in a corresponding one of a plurality of data blocks. ### Claim 18 (depends on 17) The method according to claim 17, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks. ### Claim 19 (depends on 17) The method according to claim 17, wherein the system memory comprises a random access memory. ### Claim 20 (depends on 17) The method according to claim 17, wherein the system memory comprises one or more buffers provided on one or more flash memory chips. ### Claim 21 A non-transitory machine readable medium carrying one or more sequences of instructions for writing data to a flash storage device comprising a plurality of data blocks, each data block comprising a plurality of data segments, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of: caching in a system memory of the flash storage device a plurality of data sectors to be written; writing a first one of the plurality of data sectors to a first data segment of the flash storage device; writing a first portion of a second one of the plurality of data sectors to the first data segment; and writing a second portion of the second one of the plurality of data sectors to a second data segment of the flash storage device. ### Claim 22 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the steps of: calculating error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first data segment; calculating error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second data segment; and writing the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second data segment. ### Claim 23 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the first and second ones of the plurality of data segments are data segments of a same data block of the flash storage device. ### Claim 24 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the first and second ones of the plurality of data segments are adjacent data segments. ### Claim 25 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the plurality of data sectors to be written each have a same size of 2n bits, where n is a positive integer. ### Claim 26 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the plurality of data sectors to be written each have a same size of other than 2n bits, where n is a positive integer. ### Claim 27 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the step of: updating an addressing table correlating, for each of the first and second data sectors, a logical address thereof with a physical location thereof in a corresponding one of a plurality of data blocks. ### Claim 28 (depends on 27) The non-transitory machine readable medium according to claim 27, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks. ### Claim 29 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the system memory comprises a random access memory. ### Claim 30 (depends on 21) The non-transitory machine readable medium according to claim 21, wherein the system memory comprises one or more buffers provided on one or more flash memory chips.