US 8,572,299 B2Granted

Hardware accelerator module and method for setting up same

AssigneeIntel Mobile Communications Technology Dresden GmbH

InventorsUwe Pross, Tobias Weber, Gunnar Nitsche, Thomas Fliess

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Abstract

A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

Claims4

Dependent claims

A hardware accelerator module driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the system processor, the hardware accelerator module comprising:

a register interface block adapted to receive at least one parameter set from the system processor;
an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by the at least one parameter set, and to output the processed streaming data;
and
a parameter buffering block to receive the at least one parameter set from the register interface block, adapted to consecutively store the at least one parameter set, and to sequentially provide the at least one parameter set to the accelerator core as a function of a busy state received from the accelerator core;
the parameter buffering block further adapted to provide a signal to the system processor indicative of a non-busy state of the accelerator core when the parameter buffering block is empty and the accelerator core is idle;
the parameter buffering block including first and second finite state machines, a buffer for storing the at least one parameter set, and a parameter output register coupled to the buffer and to receive the at least one parameter set, the parameter output register to provide the at least one parameter set to the accelerator core.

3 more elements

A method for setting up a hardware accelerator module, comprising the steps of:

writing, by a system processor, a first parameter set into the hardware accelerator module which first parameter set defines a first processing task of a hardware accelerator core, and emitting a first start pulse;
consecutively writing, by the system processor, a second parameter set into the hardware accelerator module which second parameter set defines a second processing task of the hardware accelerator core, wherein the writing step occurs independently from a busy status of the hardware accelerator core, and emitting a second start pulse;
sequentially buffering the parameter sets in a parameter buffer;
monitoring, by said parameter buffer, a first busy signal from the hardware accelerator core of the hardware accelerator module;
in case the hardware accelerator core is not busy, immediately passing a start pulse to the hardware accelerator core in response to the first start pulse, and providing a first parameter set to the hardware accelerator core;
in case the hardware accelerator core is busy, buffering the start signal until a non-busy indication is detected from the hardware accelerator core, and the start pulse to the hardware accelerator core and providing the first parameter set to the hardware accelerator core in response to said non-busy indication;
providing, by said parameter buffer, a signal to the system processor indicative of a non-busy state of the hardware accelerator core when the parameter buffer is empty and the hardware accelerator core is idle;
and
returning a second busy signal to the system processor wherein said second busy signal only indicates a non-busy state of the hardware accelerator module if the first busy signal indicates a non-busy condition of the hardware accelerator core and there is no further parameter set buffered in the parameter buffer, and otherwise indicates a busy state.

6 more elements

Dependencies are inferred from the claim text.