Programmable system-on-chip hub
AssigneeCypress Semiconductor Corporation
InventorsScott Allen Swindle, Warren Snyder, Drew Marshall Harrington
Life of this patent
Estimating the term…
Abstract
A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.
Claims18
A connection hub, comprising:
- one or more master processing elements;
- multiple different separately accessible busses;
- a bus connection circuit configured to enable the master processing elements to access any of the different busses simultaneously;
- multiple independently operating bus interface circuits each associated with a different one of the multiple busses, wherein the bus interface circuits are configured to reduce power consumption by the busses that are not being accessed by one of the master processing elements by powering down the busses that are not being accessed based on a first signal identifying the at least one of the busses and a second signal indicating whether the at least one of the busses is active, wherein the first signal and the second signal are generated by one of the master processing elements, and wherein the bus interface circuits are further configured to power up the at least one of the busses in response to determining that the at least one of the busses is being accessed by one of the master processing elements;
- and
- a configuration memory configured to store configuration values for the bus connection circuit and the multiple independently operating bus interface circuits.
An apparatus, comprising:
- a Central Processing Unit (CPU) interface configured to communicate with a CPU;
- a Direct Memory Access Controller (DMAC) configured to conduct Direct Memory Accesses (DMAs) independently of the CPU;
- a bus connection circuit coupled to multiple different separately accessible busses and configured to couple the CPU and the DMAC to any of the different busses at the same time, and configured to reduce power consumption by the busses that are not being accessed by the CPU or DMAC by powering down the busses that are not being accessed based on a first signal identifying at least one of the different busses and a second signal indicating whether the at least one of the different busses is active, wherein the first signal and the second signal are generated by one of the CPU or the DMAC, and further configured to power up the at least one of the busses in response to determining that the at least one of the busses is being accessed by the CPU or the DMAC;
- and
- a configuration memory configured to store configuration values for the bus connection circuit.
A programmable system on chip, comprising:
- a Central Processing Unit (CPU);
- a plurality of different busses;
- different peripheral devices;
- a hub that is configured to programmably couple the CPU to different peripheral devices over at least one of any of the multiple different busses, and to reduce power consumption by the multiple busses by powering down any of the multiple busses that are not coupled to the CPU or to different peripheral devices based on a first signal identifying the at least one of the plurality of different busses and a second signal indicating whether the at least one of the plurality of different busses is active, wherein the first signal and the second signal are generated by the CPU or by one of the different peripheral devices, and to power up the at least one of the multiple busses in response to determining that the at least one of the multiple busses is being coupled to the CPU or to the different peripheral devices;
- and
- a configuration memory configured to store configuration values for the hub.
Dependencies are inferred from the claim text.