Reduced-level two's complement arithmetic unit
AssigneeTexas Instruments Incorporated
InventorsDuc Q. Bui, Timothy D. Anderson
Life of this patent
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Abstract
A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A−B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.
Claims17
A two's complement adder, comprising:
- a first inverting selector that is arranged to perform a first inversion upon a first operand in response to a signal selecting a subtraction operation;
- a carry generator that is arranged to generate culminating generate bits for generating carry bits in response to the inverted first operand and a second operand;
- a second inverting selector that is arranged in parallel with the carry generator and that is arranged to perform in response to the signal selecting a subtraction operation a second inversion upon the results of a bit-wise logical operation of the second operand and the first inverted operand;
- and
- a sum generator that is arranged to generate a sum in response to the generated culminating generate bits and the results of the second inversion.
A processing system, comprising:
- a memory arranged in a substrate for storing instructions to be executed and for storing data to be manipulated;
- and
- at least one processor arranged in the substrate for executing the stored instructions and to manipulate the stored data, the at least one processor comprising a two's complement adder that is arranged to perform a first inversion upon a first operand in response to a signal selecting a subtraction operation, to generate culminating generate bits for generating carry bits in response to the inverted first operand and a second operand, to perform in response to the signal selecting a subtraction operation a second inversion upon the results of a bit-wise logical operation of the second operand and the first inverted operand, and to generate a sum in response to the generated culminating generate bits and the results of the second inversion.
Dependencies are inferred from the claim text.