# US 8,572,153 B1 · Multiplier circuit configurable for real or complex operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,153 B1 - Document ID: US8572153B1 - Status: Granted - Kind: B1 - Application number: 11/016,426 - Filed: 2004-12-16 - Granted: 2013-10-29 - Earliest claimed: 2004-12-16 - Assignees: Xilinx, Inc. - Applicants: Bernard J. New - Inventors: Bernard J. New - Web page: https://patentgrep.com/patent/US8572153B1 ## CPC - G06F 7/523: Multiplying only - G06F 7/4812: {Complex multiplication} - G06F 2207/3812: Devices capable of handling different types of numbers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A configurable multiplier circuit for multiplying both real and complex numbers is included in a PLD. In one embodiment, the circuit includes two adder trees. Multiplexers are used such that a conventional multiplier component is not required. The circuit is programmable to operate in one of two modes. In a first mode, the circuit multiplies the four parts of two complex numbers and outputs two values, the real portion of the product and the imaginary portion of the product. In a second mode, each of two portions of the circuit multiplies two pairs of real numbers and outputs the products. ## Claims ### Claim 1 A circuit, having inputs A, B, C, and, D, for multiplying a multiplicand by a multiplier, the circuit comprising: a first circuit portion, comprising: a first multiplexer having a first data input, a second data input, a third data input, a fourth data input, a first select input, a second select input, and a first multiplexer output, wherein A is present on the first data input, A plus a one's complement of B is present on the second data input, the one's complement of B is present on the third data input, and a value zero is present on the fourth data input; and a first adder tree having a first input, a second input, and an output, the first multiplexer output of the first circuit portion being coupled to the first input of the first adder tree, a difference of a product of A times C minus a product of B times D being output onto the output of the first adder tree; and a second circuit portion, comprising: a first multiplexer having a first data input, a second data input, a third data input, a fourth data input, a first select input, a second select input, and a first multiplexer output, wherein B is present on the first data input, B plus A is present on the second data input, A is present on the third data input, and the value zero is present on the fourth data input; and a second adder tree having a first input, a second input, and an output, the first multiplexer output of the second circuit portion being coupled to the first input of the second adder tree, a sum of a product of A times D plus a product of B times C being output onto the output of the second adder tree. ### Claim 2 (depends on 1) The circuit of claim 1, wherein A and C represent real values and B and D represent imaginary values, wherein the multiplier times the multiplicand equals a product, the product having a real part and an imaginary part, the real part being present on the output of the first adder tree of the first circuit portion, the imaginary part being present on the output of the second adder tree of the second circuit portion. ### Claim 3 (depends on 1) The circuit of claim 1, wherein each of C and D has N digits, where N is a first integer, the first circuit portion comprising N multiplexers one of which is the first multiplexer of the first circuit portion, the second circuit portion comprising N multiplexers, one of which is the first multiplexer of the second circuit portion, each of A and B having M digits, where M is a second integer, and each of the first data input, the second data input, the third data input, and the fourth data input of the N multiplexers of the first circuit portion is M+1 digits wide, and wherein each of the first data input, the second data input, the third data input, and the fourth data input of the N multiplexers of the second circuit portion is M+1 digits wide. ### Claim 4 (depends on 1) The circuit of claim 1, wherein each of A, B, C and D is a digital number in 2's complement representation. ### Claim 5 (depends on 1) The circuit of claim 1, the first circuit portion further comprising: a second multiplexer having a first data input, a second data input, a third data input, a fourth data input, a first select input, a second select input, and a data output, wherein A is present on the first data input, A plus a one's complement of B is present on the second data input, the one's complement of B is present on the third data input, and the value zero is present on the fourth data input, the data output of the second multiplexer of the first circuit portion being coupled to the second input of the first adder tree. ### Claim 6 (depends on 5) The circuit of claim 5, wherein C has a first bit and a second bit, wherein the first bit of C is supplied to one of the first select input or the second select input of the first multiplexer of the first circuit portion, and wherein the second bit of C is supplied to one of the first select input or the second select input of the second multiplexer of the first circuit portion. ### Claim 7 (depends on 1) The circuit of claim 1, wherein in a first mode, A and C represent real values, B and D represent imaginary values, the multiplicand times the multiplier equals a first product having a real part and an imaginary part, the real part being present on the output of the first adder tree, and the imaginary part being present on the output of the second adder tree, and in a second mode, the circuit multiplies four operand pairs to yield a first cross product A times C, a second cross product E times F, a third cross product G times H, and a fourth cross product D times B, wherein a first sum is present on the output of the first adder tree and a second sum is present on the output of the second adder tree, the first sum equaling the first cross product plus the second cross product and the second sum equaling the third cross product plus the fourth cross product. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the first adder tree has a third input and wherein, in the first mode, D is present on the third input of the first adder tree.