# US 8,572,151 B2 · Methods and apparatuses for cordic processing

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- Number: US 8,572,151 B2
- Document ID: US8572151B2
- Status: Granted
- Kind: B2
- Application number: 12/724,302
- Filed: 2010-03-15
- Published: 2011-09-15
- Granted: 2013-10-29
- Earliest claimed: 2010-03-15
- Assignees: Integrated Device Technology, Inc.
- Applicants: Manoj Gunwani; Harekrishna Verma
- Inventors: Manoj Gunwani; Harekrishna Verma
- Web page: https://patentgrep.com/patent/US8572151B2

## CPC

- G06F 7/5446: {using crossaddition algorithms, e.g. CORDIC}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

## Claims

### Claim 1

A CORDIC engine, comprising:
an N-stage CORDIC processor configured for performing N micro-iterations and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input, the N-stage CORDIC processor comprising N CORDIC processors operably cascaded in series, each of the CORDIC processors comprising:
a first variable shifter operably coupled to a first vector input and configured to generate a shifted first vector by an amount responsive to an iteration indicator from the counter;
a second variable shifter operably coupled to a second vector input and configured to generate a shifted second vector by an amount responsive to the iteration indicator from the counter;
a first adder/subtractor for arithmetically combining the first vector input and the shifted second vector to generate a first vector output;
a second adder/subtractor for arithmetically combining the second vector input and the shifted first vector to generate a second vector output; and
a third adder/subtractor for arithmetically combining a third vector input and a elementary angle input correlated to the iteration indicator to generate a third vector output;
a counter configured for counting a number of M macro-iterations and indicating a start of the cycle iterations; and
a multiplexer configured for selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times;
wherein the 3-vector CORDIC output is configured to be complete after N*M clock cycles by generating the N micro-iterations for each of the M macro-iterations.

### Claim 2 (depends on 1)

The CORDIC engine of claim 1, wherein each of the M macro-iterations are configured to be a clock period long and the N micro-iterations are configured to be performed in less than or equal to the clock period.

### Claim 3 (depends on 1)

The CORDIC engine of claim 1, further comprising a storage buffer for providing elementary angle inputs to the N-stage CORDIC processor for each of the N micro-iterations.

### Claim 4 (depends on 1)

The CORDIC engine of claim 1, further comprising a programmable logic routing block configured for interfacing the 3-vector CORDIC input and the 3-vector CORDIC output to an additional CORDIC engine, a programmable logic array, or a combination thereof.

### Claim 5 (depends on 1)

The CORDIC engine of claim 1, further comprising a 3-vector register operably coupled between the 3-vector CORDIC input and a first CORDIC processor in the series of N CORDIC processors.

### Claim 6 (depends on 1)

The CORDIC engine of claim 1, further comprising a 3-vector register operably coupled between a last CORDIC processor in the series of N CORDIC processors and the 3-vector CORDIC output.

### Claim 7 (depends on 1)

The CORDIC engine of claim 1, wherein the first variable shifter and the second variable shifter each comprise:
a first shifter configured for shifting by a multiple of N; and
a second shifter configured for shifting by a value between one and N or a value between 0 and N−1.

### Claim 8 (depends on 1)

The CORDIC engine of claim 1, further comprising an add/subtract determiner configured to select a mode of add or subtract for at least one of the first adder/subtractor, the second adder/subtractor, and the third adder/subtractor responsive to at least one of a sign bit of the second vector input and a sign bit of the third vector input.

### Claim 9 (depends on 8)

The CORDIC engine of claim 8, further comprising an arithmetic function modifier configured for modifying the mode of add or subtract for the first adder/subtractor responsive to a mode input.

### Claim 10

A programmable logic array, comprising:
a plurality of programmable logic blocks configured to be programmable for a variety of interconnections and a variety of functions; and
a CORDIC engine operably coupled to at least some of the plurality of programmable logic blocks, the CORDIC engine comprising:
an N-stage CORDIC processor configured for performing N micro-iterations and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input, the N-stage CORDIC processor comprising N CORDIC processors operably cascaded in series, each of the CORDIC processors comprising:
a first variable shifter operably coupled to a first vector input and configured to generate a shifted first vector by an amount responsive to an iteration indicator from the counter;
a second variable shifter operably coupled to a second vector input and configured to generate a shifted second vector by an amount responsive to the iteration indicator from the counter;
a first adder/subtractor for arithmetically combining the first vector input and the shifted second vector to generate a first vector output;
a second adder/subtractor for arithmetically combining the second vector input and the shifted first vector to generate a second vector output; and
a third adder/subtractor for arithmetically combining a third vector input and a elementary angle input correlated to the iteration indicator to generate a third vector output;
a counter configured for counting a number of M macro-iterations and indicating a start of the cycle iterations; and
a multiplexer configured for selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times;
wherein the 3-vector CORDIC output is configured to be complete after N*M clock cycles by generating the N micro-iterations for each of the M macro-iterations.

### Claim 11 (depends on 10)

The programmable logic array of claim 10, wherein each of the M macro-iterations are configured to be a clock period long and the N micro-iterations are configured to be performed in less than or equal to the clock period.

### Claim 12 (depends on 10)

The programmable logic array of claim 10, further comprising a storage buffer for providing elementary angle inputs to the N-stage CORDIC processor for each of the N micro-iterations.

### Claim 13 (depends on 10)

The programmable logic array of claim 10, further comprising a routing block configured for interfacing the 3-vector CORDIC input and the 3-vector CORDIC output to an additional CORDIC engine, a programmable logic array, or a combination thereof.

### Claim 14 (depends on 10)

The programmable logic array of claim 10, further comprising a 3-vector register operably coupled between the 3-vector CORDIC input and a first CORDIC processor in the series of N CORDIC processors.

### Claim 15 (depends on 10)

The programmable logic array of claim 10, further comprising a 3-vector register operably coupled between a last CORDIC processor in the series of N CORDIC processors and the 3-vector CORDIC output.

### Claim 16 (depends on 10)

The programmable logic array of claim 10, wherein the first variable shifter and the second variable shifter each comprise:
a first shifter configured for shifting by a multiple of N; and
a second shifter configured for shifting by a value between one and N or a value between 0 and N−1.

### Claim 17

A method, comprising:
performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input by:
variably shifting a first vector input to generate a shifted first vector by an amount responsive to an iteration indicator from the counting the number of M macro-iterations;
variably shifting a second vector input to generate a shifted second vector by an amount responsive to the iteration indicator;
adding or subtracting the first vector input and the shifted second vector to generate a first vector output;
adding or subtracting the second vector input and the shifted first vector to generate a second vector output; and
adding or subtracting a third vector input and a elementary angle input correlated to the iteration indicator to generate a third vector output;
counting a number of M macro-iterations for the CORDIC algorithm and indicating a start of the cycle iterations;
repeating the performing the N micro-iterations for each of the M macro-iterations; and
selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of the M macro-iterations are a clock period long and the N micro-iterations are performed in less than or equal to the clock period.

### Claim 19 (depends on 17)

The method of claim 17, further comprising providing elementary angle inputs for each of the N micro-iterations.

### Claim 20 (depends on 17)

The method of claim 17, further comprising interfacing the 3-vector CORDIC input and the 3-vector CORDIC output to an additional CORDIC engine, a programmable logic array, or a combination thereof.

### Claim 21 (depends on 17)

The method of claim 17, further comprising storing the 3-vector CORDIC input in a 3-vector register.

### Claim 22 (depends on 17)

The method of claim 17, further comprising storing the 3-vector CORDIC output in a 3-vector register.

### Claim 23 (depends on 17)

The method of claim 17, wherein the variably shifting the first vector input and variably shifting the second vector input each comprise:
shifting by a multiple of N; and
shifting by a value between one and N or a value between 0 and N−1.

### Claim 24 (depends on 17)

The method of claim 17, further comprising selecting a mode of add or subtract for at least one of the adding or subtracting the first vector input, the adding or subtracting the second vector input, and the adding or subtracting the third vector input responsive to at least one of a sign bit of the second vector input and a sign bit of the third vector input.

### Claim 25 (depends on 24)

The method of claim 24, further comprising modifying the mode of add or subtract for the adding or subtracting the first vector input responsive to a mode input.