Method for implementing a bit-reversed increment in a data processing system

A data processing system having a processor for executing instructions and a memory for storing a plurality of elements to be accessed in a bit-reversed order, the processor executing a predetermined one of the instructions to form a new address by:

• receiving the predetermined one of the instructions at an input of the processor;
• storing a first address in an instruction storage circuit, wherein the first address is an address of a bit-reversed addressing sequence and directly addresses a first element of the plurality of elements;
• providing a specifier that indicates both a first portion of the first address and a second portion of the first address, the first portion of the first address is identified to be modified by the processor and the second portion of the first address is identified to remain unchanged, wherein the specifier includes a same number of bits as the first address;
• decoding the predetermined one of the instructions and in response to the decoding, the processor modifying the first portion of the first address by performing a bit-reversed increment to form a modified first portion, the processor using all bits of the specifier to form a first intermediate value representative of the modified first portion, and the processor using all bits of the specifier to form a second intermediate value representative of the second portion using all bits of the specifier;
• combining the modified first portion with the second portion of the first address which remained unchanged to form a second address as the new address, wherein the step of combining is performed such that a final operation used to form the new address is a bit-wise OR operation of the first intermediate value and the second intermediate value, and wherein the second address is an immediately subsequent address to the first address in the bit-reversed addressing sequence and directly addresses an immediately subsequent element of the plurality of elements in accordance with the bit-reversed order;
• and
• storing the second address in a first storage circuit, the processor using the second address when executing a subsequent instruction to access the memory.

A data processing system comprising:

• a communication bus;
• a processor coupled to the communication bus, the processor executing a plurality of data processing instructions;
• and
• a memory coupled to the communication bus, the memory storing the plurality of data processing instructions wherein one of the plurality of data processing instructions functions to update a first pointer value, the one of the plurality of data processing instructions comprising:
• a register selector field for selecting a register to provide a specifier that indicates both a first portion of the first pointer value and a second portion of the first pointer value, the first portion of the first pointer value is identified to be modified by the processor and the second portion of the first pointer value is identified to remain unchanged, wherein a first change in bit value from a first bit value to a second bit value in the specifier when the specifier is traversed from a highest order bit down towards a lowest order bit defines a boundary between the second portion and the first portion, wherein the specifier includes a same number of bits as the first pointer value and includes at least one higher order bit that has the first bit value;
• the processor further comprising:
• an execution unit for decoding the one of the plurality of data processing instructions and in response to the decoding, the processor modifying the first portion of the value by performing a bit-reversed increment to form a modified first portion, using all bits of the specifier to form a first intermediate value representative of the modified first portion, and using all bits of the specifier to form a second intermediate value representative of the second portion using all bits of the specifier, and the execution unit combining the modified first portion with the second portion of the value which remained unchanged to form a second pointer value, wherein the combining is performed such that a final operation used to form the second pointer value is a bit-wise OR operation of the first intermediate value and the second intermediate value;
• and
• a register file coupled to the execution unit, the register file storing the second pointer value, the processor using the second pointer value when executing a subsequent instruction to access the memory.