Efficiency of static core turn-off in a system-on-a-chip with variation

A processor-implemented method for improving efficiency of a core turn-off in a physical multi-core processor with variation, wherein the physical multi-core processor is based upon a multi-core processor design, the method comprising:

• determining via a simulation at a design stage a condition for core turn-off for a certain core of the multi-core processor design;
• assessing whether the condition matches an actual variation in the certain core of the physical multi-core processor, the actual variation measured at a testing stage of the physical multi-core processor;
• providing a core turn-off list based on the matching of the condition and the actual variation in the certain core;
• and
• selecting a core of the physical multi-core processor to turn off based on the contents of the turn-off list.

A computer system for improving efficiency of a core turn-off in a physical multi-core processor with variation, wherein the physical multi-core processor is based upon a multi-core processor design, the system comprising:

• a computer memory;
• a processor in communications with the computer memory, wherein the computer system is capable of performing a method comprising:
• conducting via a simulation a turn-off analysis of the multi-core processor design at a design stage, wherein the turn-off analysis of the multi-core processor design includes a first output corresponding to a core of the multi-core processor design to turn off;
• conducting a turn-off analysis of the physical multi-core processor at a testing stage, wherein the turn-off analysis of the physical multi-core processor includes a second output corresponding to a core of the physical multi-core processor to turn off;
• comparing the first output and the second output to determine if the core referred to by the first output is the same core as the core referred to by the second output;
• and
• outputting a third output corresponding to the core referred to by both the first output and the second output if the comparing indicates that the core referred to by the first output is the same core as the core referred to by the second output.

A computer program product for improving efficiency of a core turn-off in a physical multi-core processor with variation, wherein the physical multi-core processor is based upon a multi-core processor design, the computer program product comprising:

• a storage device readable by a processing circuit and storing instructions for execution by the processing circuit, wherein said storage device is not propagating signal, for performing a method comprising:
• conducting via a simulation a turn-off analysis of the multi-core processor design at a design stage, wherein the turn-off analysis of the multi-core processor design includes a first output corresponding to a core of the multi-core processor design to turn off;
• conducting a turn-off analysis of the physical multi-core processor at a testing stage, wherein the turn-off analysis of the physical multi-core processor includes a second output corresponding to a core of the physical multi-core processor to turn off;
• comparing the first output and the second output to determine if the core referred to by the first output is the same core as the core referred to by the second output;
• and
• outputting a third output corresponding to the core referred to by both the first output and the second output if the comparing indicates that the core referred to by the first output is the same core as the core referred to by the second output.

A processor-implemented method for improving efficiency of a core turn-off in a physical multi-core processor with variation and a plurality of power modes, wherein the physical multi-core processor is based upon a multi-core processor design, the method comprising:

• conducting via a simulation a turn-off analysis of the multi-core processor design at a design stage, wherein the turn-off analysis of the multi-core processor design includes a first output corresponding to a core of the multi-core processor design to turn off and wherein the first output is stored in a data structure performing a function of a look-up table;
• conducting a turn-off analysis of the physical multi-core processor at a testing stage, wherein the turn-off analysis of the physical multi-core processor includes a second output corresponding to a core of the physical multi-core processor to turn off;
• comparing the first output and the second output to determine if the core referred to by the first output is the same core as the core referred to by the second output;
• and
• outputting a third output corresponding to the core referred to by both the first output and the second output if the comparing indicates that the core referred to by the first output is the same core as the core referred to by the second output.