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US 8,571,822 B2Granted
Method and device for analyzing the behavior of a power supply in a circuit
AssigneeSTMicroelectronics (Grenoble 2) SAS
InventorHerve Le-Gall
Life of this patent
Estimating the term…
Abstract
A method for testing an integrated circuit, the method including performing a series of at least three tests, each including: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken.
Claims30
A method, comprising:
- selecting a series of at least three tests of an integrated circuit;
- performing, using the integrated circuit, the selected series of at least three tests on the integrated circuit, each test comprising:
- selecting two nodes among at least three taking nodes for taking clock signals, from the integrated circuit;
- taking two clock signals at the two selected taking nodes during a test duration;
- detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration;
- and
- determining from numbers of events counted, a test result proportional to a sum of jitter variances of the two clock signals taken during the test duration, wherein a set of two nodes selected during one of the series of tests is different from a set of two nodes selected during another one of the series of tests;
- and
- determining, using the at least one processing device of the integrated circuit, a jitter variance of each clock signal taken during the series of tests using a matrix calculation based on the results of the series of tests.
6 more elements
An integrated circuit, comprising:
- at least one clock generator configured to generate a clock signal;
- at least three clock signal taking nodes;
- and
- analysis logic configured to:
- receive test control signals of a test of the integrated circuit;
- select, based on the test control signals, two clock signal taking nodes among the at least three taking nodes, wherein the analysis logic includes one or more multiplexers coupled to the at least three clock signal taking nodes and configured to select the two clock signal taking nodes based on the test control signals;
- take two clock signals at the two selected clock signal taking nodes during a test duration;
- and
- detect and count events appearing in a jitter signal between the two clock signals taken, during the test duration.
6 more elements
A testing device, comprising:
- a connection interface configured to couple to an integrated circuit;
- and
- testing logic coupled to the connection interface and configured to:
- perform a series of at least three tests, each test comprising:
- generating test control signals to control selection by the integrated circuit, of two nodes among at least three clock signal taking nodes;
- generating test control signals to control taking by the integrated circuit of two clock signals at the two selected taking nodes, during a test duration, and detecting and counting by the integrated circuit of events appearing in a jitter signal between the two taken clock signals, during the test duration;
- and
- determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, wherein each of the at least three clock signal taking nodes is selected for at least one of the tests of the series of at least three tests;
- and
- determine a jitter variance of each clock signal taken during the series of tests using a matrix calculation based on the determined test results of the series of tests.
7 more elements
A system, comprising:
- an integrated circuit, having:
- at least one clock signal generator;
- at least three clock signal taking nodes;
- and
- supply voltage integrity analysis logic including:
- a multiplexer coupled to the at least three clock signal taking nodes and configured to select, based on received test control signals, two clock signal taking nodes among the at least three taking nodes;
- and
- a jitter measurement block configured to detect and count events appearing in a jitter signal between the two clock signals selected by the multiplexer during the test duration;
- and
- a testing device configured to generate the test control signals and to receive numbers of events counted by the supply voltage integrity analysis logic.
7 more elements
A non-transitory computer-readable medium whose contents cause at least one processing device to perform a method, the method comprising:
- selecting a series of at least three tests of an integrated circuit;
- performing the selected series of at least three tests on the integrated circuit, each test comprising:
- selecting two nodes among at least three taking nodes for taking clock signals, from the integrated circuit;
- taking two clock signals at the two selected taking nodes during a test duration;
- detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration;
- and
- determining from numbers of events counted, a test result proportional to a sum of jitter variances of the two clock signals taken during the test duration, wherein each of the at least three clock signal taking nodes is selected for at least one of the tests of the series of at least three tests;
- and
- determining a jitter variance of each clock signal taken during the series of tests using a matrix calculation based on the results of the series of tests.
6 more elements
A system, comprising:
- means for selecting a series of at least three tests of an integrated circuit;
- means for performing the selected series of at least three tests on the integrated circuit, each test comprising:
- selecting two nodes among at least three taking nodes for taking clock signals, from the integrated circuit;
- taking two clock signals at the two selected taking nodes during a test duration;
- detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration;
- and
- determining from numbers of events counted, a test result proportional to a sum of jitter variances of the two clock signals taken during the test duration, wherein each of three clock signal taking nodes is selected for at least one of the tests of the series of at least three tests;
- and
- means for determining a jitter variance of each clock signal taken during the series of tests using a matrix calculation based on the results of the series of tests.
6 more elements
Dependencies are inferred from the claim text.