System and method to reduce pre-back-grinding process defects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Fa Lu, Cheng-Ting Chen, James Hu, Chung-Shi Liu
Life of this patent
Estimating the term…
Abstract
Processing defects arising during processing of a semiconductor wafer prior to back-grinding are reduced with systems and methods of sensor placement. One or more holes are bored into a chuck table for receiving semiconductor wafers, or a support table next to the chuck table. One or more sensors are disposed in the holes for monitoring parameters during a pre-back-grinding (PBG) process. A control box converts a set of signals received from the sensors. A computer-implemented process control tool receives the converted set of signals from the control box and determines whether the PBG process will continue.
Claims20
A system for reducing processing defects during processing of a semiconductor wafer prior to back-grinding the wafer, the system comprising:
- a table having one or more holes formed therein, wherein the table is one of a chuck table or a support table, and wherein the holes are perpendicular to the surface upon which a pre-back-grinding (PBG) process occurs;
- one or more sensors disposed in said holes for monitoring a parameter during the PBG process;
- a control box communicatively coupled with one or more sensors and configured to convert a set of received signals from the one or more sensors into digital form;
- and
- a computer-implemented process control tool coupled with the control box and configured to determine whether the PBG process will continue based on the digital form of the sensor signals.
A method of reducing warpage to and breakage of a semiconductor wafer caused by a pre-back-grinding (PBG) process, the method comprising:
- receiving a semiconductor wafer at a PBG apparatus having one or more holes formed therein, wherein the holes are perpendicular to the surface upon which the semiconductor wafers are placed and containing one or more sensors in said holes;
- measuring one or more parameters associated with said PBG processes, thereby resulting in one or more measured PBG parameters;
- converting the measured PBG parameters into a digital format by a control box;
- determining if the digital format of the measured PBG parameters fall within a specified range of acceptable process values;
- and
- pausing the PBG process if the parameters do not fall within the specified range of acceptable values.
A system for reducing processing defects arising during processing of a semiconductor wafer prior to back-grinding in a flip chip ball grid array process, the system comprising:
- a chuck table for receiving semiconductor wafers and a support table, wherein the chuck table or the support table have one or more holes constructed therein by computer numerical control lathes, wherein the holes are perpendicular to the surface upon which the semiconductor wafers are received;
- one or more sensors disposed in said holes for monitoring pressure and speed parameters during tape lamination prior to back-grinding the semiconductor wafers;
- a control box receiving a set of signals from the one or more sensors;
- and
- a computer-implemented process control tool arranged to pause the tape lamination responsive to determining that a received set of signals from the control box, in comparison with a corresponding set of acceptable ranges, is outside the acceptable ranges.
Dependencies are inferred from the claim text.