# US 8,571,510 B2 · High linearity low noise receiver with load switching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,571,510 B2 - Document ID: US8571510B2 - Status: Granted - Kind: B2 - Application number: 12/193,695 - Filed: 2008-08-18 - Published: 2010-02-18 - Granted: 2013-10-29 - Earliest claimed: 2008-08-18 - Assignees: QUALCOMM Incorporated - Applicants: Li Liu; Prasad S. Gudem - Inventors: Li Liu; Prasad S. Gudem - Web page: https://patentgrep.com/patent/US8571510B2 ## CPC - H03F 1/32: Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) - H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers} - H03F 1/223: {with MOSFET's} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/45188: {Non-folded cascode stages} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H04B 1/109: {by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input} - H04B 1/18: Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/336: A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit - H03F 2203/45386: the AAC comprising one or more coils in the source circuit - H03F 2203/45394: the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier - H03F 2203/45726: the LC comprising more than one switch, which are not cross coupled - H03F 2203/7206: the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier - H03F 2203/7236: the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es) - H03F: AMPLIFIERS - H04B: TRANSMISSION ## Abstract A receiver includes a low noise amplifier (LNA) and multiple pairs of mixers. The LNA receives and amplifies an LNA input signal and provides at least one LNA output signal. Each pair of mixers downconverts one of the at least one LNA output signal when enabled. Each pair of mixers may be selectively enabled or disabled, e.g., based on a mode selected from among multiple modes. In one design, the LNA includes multiple load sections coupled in parallel. Each load section may be selectively enabled or disabled, e.g., based on the selected mode. In one design, first and second pairs of mixers and first and second load sections may be enabled for a high linearity mode. The first pair of mixers and the first load section may be enabled and the second pair of mixers and the second load section may be disabled for a low linearity mode. ## Claims ### Claim 1 An apparatus comprising: a low noise amplifier (LNA) configured to receive an LNA input signal and provide at least one LNA output signal, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and multiple pairs of mixers coupled to the LNA, each pair of mixers configured to downconvert one LNA output signal when enabled, each pair of mixers being selectively enabled or disabled; wherein the multiple pairs of mixers have variable mixer input impedance, and selective enabling and disabling of each pair of mixers increases apparatus linearity by varying mixer input impedance. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the multiple pairs of mixers comprise first and second pairs of mixers implemented with transistors of different sizes. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the multiple pairs of mixers comprise first and second pairs of mixers biased with different amounts of current or different bias voltages. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the multiple pairs of mixers comprise first and second pairs of mixers driven with local oscillator (LO) signals of different signal levels. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the multiple pairs of mixers have outputs coupled together and providing a downconverted signal. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein each pair of mixers is enabled or disabled based on a mode selected from among multiple modes, each mode being associated with a different set of at least one pair of mixers, and wherein the at least one pair of mixers associated with the selected mode is enabled and all remaining pairs of mixers, if any, are disabled. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the first and second pairs of mixers are enabled for a high linearity mode, and wherein the first pair of mixers is enabled and the second pair of mixers is disabled for a low linearity mode. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the high linearity mode is selected when a large jammer is detected and the low linearity mode is selected when a large jammer is not detected. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the LNA is configured to provide a single LNA output signal, and wherein each pair of mixers is configured to downconvert the LNA output signal when enabled. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the LNA is configured to provide multiple LNA output signals, one LNA output signal for each pair of mixers, and wherein each pair of mixers is configured to downconvert a respective LNA output signal when enabled. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the LNA is configured to provide first and second LNA output signals, wherein the first pair of mixers is configured to downconvert the first LNA output signal when enabled, and wherein the second pair of mixers is configured to downconvert the second LNA output signal when enabled. ### Claim 12 An apparatus comprising: a low noise amplifier (LNA) comprising an input stage and an output stage, the input stage receiving an LNA input signal and providing an amplified signal, the output stage buffering the amplified signal and providing at least one LNA output signal, the output stage comprising multiple load sections coupled in parallel, each load section configured to be selectively enabled or disabled; wherein the apparatus is configured to vary internal and external loads of the LNA by selectively enabling and disabling each load section; wherein the input stage comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel and each load section comprises a plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein each of the multiple load sections comprises a pair of P-channel metal oxide semiconductor (PMOS) transistors coupled to a pair of N-channel metal oxide semiconductor (NMOS) transistors. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the multiple load sections are implemented with transistors of different sizes. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the multiple load sections are biased with different amounts of current or different bias voltages. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the multiple load sections are configured to provide multiple LNA output signals, one LNA output signal for each load section. ### Claim 17 (depends on 12) The apparatus of claim 12, wherein the multiple load sections comprise first and second load sections, wherein the first and second load sections are enabled for a high linearity mode, and wherein the first load section is enabled and the second load section is disabled for a low linearity mode. ### Claim 18 An apparatus comprising: a low noise amplifier (LNA) configured to receive an LNA input signal and provide multiple LNA output signals, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and multiple pairs of mixers coupled to the LNA, each pair of mixers configured to downconvert a different one of the multiple LNA output signals when enabled; wherein the multiple pairs of mixers have variable mixer input impedance, and selective enabling and disabling of each pair of mixers increases apparatus linearity by varying mixer input impedance. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein each pair of mixers is enabled or disabled based on a mode selected from among multiple modes. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the LNA comprises multiple load sections configured to provide the multiple LNA output signals, each load section being enabled or disabled based on the selected mode. ### Claim 21 (depends on 18) The apparatus of claim 18, wherein the LNA comprises first and second load sections configured to provide first and second LNA output signals for the first and second pairs of mixers, respectively. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the first and second load sections and the first and second pairs of mixers are enabled for a high linearity mode, and wherein the first load section and the first pair of mixers are enabled and the second load section and the second pair of mixers are disabled for a low linearity mode. ### Claim 23 An integrated circuit comprising: a low noise amplifier (LNA) configured to receive an LNA input signal and provide at least one LNA output signal, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and multiple pairs of mixers coupled to the LNA, each pair of mixers configured to downconvert one of the at least one LNA output signal when enabled, each pair of mixers being selectively enabled or disabled; wherein the multiple pairs of mixers have variable mixer input impedance, and selective enabling and disabling of each pair of mixers increases integrated circuit linearity by varying mixer input impedance. ### Claim 24 (depends on 23) The integrated circuit of claim 23, wherein the first and second pairs of mixers are enabled for a high linearity mode, and wherein the first pair of mixers is enabled and the second pair of mixers is disabled for a low linearity mode. ### Claim 25 (depends on 23) The integrated circuit of claim 23, wherein the LNA comprises multiple load sections coupled in parallel, each load section being selectively enabled or disabled. ### Claim 26 (depends on 25) The integrated circuit of claim 25, wherein the multiple load sections comprise first and second load sections, wherein the first and second load sections are enabled for a high linearity mode, and wherein the first load section is enabled and the second load section is disabled for a low linearity mode. ### Claim 27 (depends on 25) The integrated circuit of claim 25, wherein the multiple load sections comprise first and second load sections, wherein the first and second load sections and the first and second pairs of mixers are enabled for a high linearity mode, and wherein the first load section and the first pair of mixers are enabled and the second load section and the second pair of mixers are disabled for a low linearity mode. ### Claim 28 A method of operating a receiver, comprising: selecting a mode from among multiple modes based on detected operating conditions; enabling at least one pair of mixers among multiple pairs of mixers based on the selected mode; disabling remaining ones of the multiple pairs of mixers, if any, based on the selected mode; enabling at least one load section among multiple load sections of a low noise amplifier (LNA) based on the selected mode, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and disabling remaining ones of the multiple load sections, if any, based on the selected mode. ### Claim 29 (depends on 28) The method of claim 28, wherein the enabling at least one pair of mixers and the disabling remaining ones of the multiple pairs of mixers comprise enabling the first and second pairs of mixers if a high linearity mode is selected, and enabling the first pair of mixers and disabling the second pair of mixers if a low linearity mode is selected. ### Claim 30 (depends on 28) The method of claim 28, wherein the multiple load sections comprise first and second load sections, and wherein the enabling at least one load section and the disabling remaining ones of the multiple load sections comprise enabling the first and second load sections if a high linearity mode is selected, and enabling the first load section and disabling the second load section if a low linearity mode is selected. ### Claim 31 (depends on 28) The method of claim 28, wherein the selecting a mode comprises detecting for large jammer, selecting a high linearity mode if large jammer is detected, and selecting a low linearity mode if large jammer is not detected. ### Claim 32 An apparatus comprising: means for selecting a mode from among multiple modes based on detected operating conditions; means for enabling at least one pair of mixers among multiple pairs of mixers based on the selected mode; and means for disabling remaining ones of the multiple pairs of mixers, if any, based on the selected mode; means for enabling at least one load section among multiple load sections of a low noise amplifier (LNA) based on the selected mode, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and means for disabling remaining ones of the multiple load sections, if any, based on the selected mode. ### Claim 33 (depends on 32) The apparatus of claim 32, wherein the means for enabling at least one pair of mixers and the means for disabling remaining ones of the multiple pairs of mixers comprise means for enabling the first and second pairs of mixers if a high linearity mode is selected, and means for enabling the first pair of mixers and disabling the second pair of mixers if a low linearity mode is selected. ### Claim 34 (depends on 32) The apparatus of claim 32, wherein the multiple load sections comprise first and second load sections, and wherein the means for enabling at least one load section and the means for disabling remaining ones of the multiple load sections comprise means for enabling the first and second load sections if a high linearity mode is selected, and means for enabling the first load section and disabling the second load section if a low linearity mode is selected. ### Claim 35 (depends on 32) The apparatus of claim 32, wherein the means for selecting a mode comprises means for detecting for large jammer, means for selecting a high linearity mode if large jammer is detected, and means for selecting a low linearity mode if large jammer is not detected. ### Claim 36 A computer program product embodied with executable instructions, the executable instructions comprising: code for causing at least one computer to select a mode from among multiple modes based on detected operating conditions; code for causing the at least one computer to enable at least one pair of mixers among multiple pairs of mixers based on the selected mode; and code for causing the at least one computer to disable remaining ones of the multiple pairs of mixers, if any, based on the selected mode; code for enabling at least one load section among multiple load sections of a low noise amplifier (LNA) based on the selected mode, wherein the LNA comprises a plurality of N-channel metal oxide semiconductor (NMOS) transistors connected in parallel, and a separate plurality of NMOS transistors and a plurality of P-channel metal oxide semiconductor (PMOS) transistors; and code for disabling remaining ones of the multiple load sections, if any, based on the selected mode. ### Claim 37 (depends on 36) The computer program product of claim 36, wherein the code for enabling at least one pair of mixers and the code for disabling remaining ones of the multiple pairs of mixers comprise code for enabling the first and second pairs of mixers if a high linearity mode is selected, and code for enabling the first pair of mixers and disabling the second pair of mixers if a low linearity mode is selected.