Back to results
US 8,571,502 B2Granted
Adjusting PLL clock source to reduce wireless communication interference
AssigneeApple Inc.
InventorMichael Frank
Life of this patent
Estimating the term…
Abstract
Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.
Claims23
A clock generation unit comprising:
- a random modulator configured to receive current clock frequency information corresponding to a current clock frequency, and generate a divisor output based on the received current clock frequency information;
- a clock divider circuit configured to:
- receive the divisor output from the random modulator;
- receive an input clock having an input frequency;
- and
- generate a reference clock signal for a phase locked loop (PLL) by dividing the input frequency of the input clock by the divisor, wherein the reference clock signal has the current frequency;
- and
- first circuitry configured to:
- receive updated clock frequency information and a transition value, wherein the updated clock frequency information corresponds to an updated clock frequency that is different from the current clock frequency;
- adjust the clock frequency information based on the updated clock frequency information;
- and
- cause the PLL to retain lock with the reference clock signal by adjusting the clock frequency information according to the transition value when adjusting the clock frequency information based on the updated clock frequency information.
9 more elements
A method for generating a clock signal for a phase locked loop (PLL) with reduced radio frequency (RF) interference, the method comprising:
- receiving first clock frequency information, wherein the first clock frequency information is usable to generate a first clock frequency, wherein the first clock frequency is different than a current clock frequency;
- modifying the first clock frequency information to produce second clock frequency information according to transition information, wherein the second clock frequency information is usable to generate a second clock frequency, wherein the second clock frequency is different than the first clock frequency, wherein modifying the first clock frequency information according to the transition information prevents the PLL from losing lock;
- modifying the second clock frequency information to generate a divisor;
- dividing an input clock according to the divisor to generate a clock signal, wherein the clock signal varies around the second clock frequency based on said modifying the second clock frequency information;
- and
- providing the clock signal to the PLL;
- wherein said receiving the first clock information, said modifying the first clock frequency information to produce the second clock frequency information, said modifying the second clock frequency information, said dividing the input clock, and said providing the clock signal to the PLL are performed for a plurality of iterations.
4 more elements
A system, comprising:
- a clock divider circuit configured to receive an input clock and to divide a frequency of the input clock by a divisor to generate a reference clock for a phase locked loop (PLL);
- a first circuit configured to:
- receive first clock frequency information, wherein the first clock frequency information is usable to generate a first clock frequency, wherein the first clock frequency is different than a current clock frequency;
- modify the first clock frequency information according to transition information and produce second clock frequency information based on the modified first clock frequency information, wherein modifying the first frequency information according to the transition information prevents the PLL from losing lock, wherein the second clock frequency information is usable to generate a second clock frequency, and wherein the second clock frequency is different than the first clock frequency;
- a random modulator coupled to the first circuit and the clock divider circuit and configured to randomly modify the second frequency information, and generate the divisor based on the randomly modified second frequency information, wherein the reference clock varies around the second clock frequency based on the random modulator modifying the second clock frequency information;
- and
- an oscillator configured to generate an oscillator output signal that modifies a third clock frequency information over time to generate the first clock frequency information, and consequently causes a frequency of the reference clock to vary over time around a desired clock frequency.
4 more elements
A mobile device, comprising:
- a display;
- display circuitry coupled to the display, wherein the display circuitry is configured to control graphics output to the display of the mobile device;
- a high speed serial interface (HSSI) coupled to the display circuitry, wherein the HSSI comprises a phase locked loop (PLL), wherein the PLL is configured to receive an input clock signal and output an HSSI clock signal, wherein the display circuitry operates according to the HSSI clock signal;
- an antenna for performing wireless communication using a plurality of wireless channels, wherein harmonics of the HSSI clock overlap with one or more of the wireless channels;
- a first clock, wherein the first clock is configured to output a first clock signal;
- an oscillator, wherein the oscillator is configured to produce an oscillating signal;
- a filter coupled to the oscillator, wherein the filter is configured to produce a filtered divisor based on input derived from the oscillating signal and a first divisor, wherein the filtered divisor is modified from the input such that the PLL retains lock;
- a modulator coupled to the filter, wherein the modulator is configured to provide a modulated divisor based on the filtered divisor, wherein the modulated divisor varies around the filtered divisor;
- a divider coupled to the modulator, wherein the divider is configured to divide the first clock signal by the filtered divisor to produce the input clock signal to the PLL;
- wherein the oscillator, the filter, the modulator, and the divider operate to reduce interference of the HSSI clock with the wireless communication.
7 more elements
Dependencies are inferred from the claim text.