# US 8,571,170 B2 · Shift register circuit

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- Number: US 8,571,170 B2
- Document ID: US8571170B2
- Status: Granted
- Kind: B2
- Application number: 13/718,438
- Filed: 2012-12-18
- Published: 2013-05-02
- Granted: 2013-10-29
- Earliest claimed: 2010-05-10
- Assignees: Mitsubishi Electric Corporation
- Applicants: Youichi Tobita
- Inventors: Youichi Tobita
- Web page: https://patentgrep.com/patent/US8571170B2

## CPC

- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2320/0252: Improving the response speed
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).

## Claims

### Claim 1

A shift register circuit comprising:
first and second input terminals, first and second output terminals, and first and second clock terminals;
first and second voltage signal terminals respectively supplied with first and second voltage signals that are complementary to each other;
a first transistor that supplies said first output terminal with a first clock signal inputted to said first clock terminal;
a second transistor that supplies said second output terminal with a second clock signal inputted to said second clock terminal;
a third transistor that supplies said first voltage signal to a first node to which a control electrode of said first transistor connects or a second node to which a control electrode of said second transistor connects, in response to activation of a first input signal inputted to said first input terminal;
a fourth transistor that supplies said second voltage signal to said first node or said second node in response to activation of a second input signal inputted to said second input terminal; and
a fifth transistor connected between said first node and said second node, wherein
said first clock signal and said second clock signal have a same phase, and a setting is possible such that only said second clock signal is activated and the first clock signal is kept at an inactive level in a particular period.

### Claim 2 (depends on 1)

The shift register circuit according to claim 1, wherein a control electrode of said fifth transistor is connected to a power supply of a given potential that is not more than an active level of said second clock signal.

### Claim 3 (depends on 1)

The shift register circuit according to claim 1, wherein, when said second output terminal is charged, said fifth transistor electrically separates said first node and second node.

### Claim 4 (depends on 1)

The shift register circuit according to claim 1, further comprising:
a sixth transistor that discharges said first output terminal; and
a seventh transistor that discharges said second output terminal;
wherein a control electrode of said sixth transistor and a control electrode of said seventh transistor are connected to each other.