# US 8,571,159 B1 · Apparatus and methods for high-speed interpolator-based clock and data recovery

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- Number: US 8,571,159 B1
- Document ID: US8571159B1
- Status: Granted
- Kind: B1
- Application number: 13/310,513
- Filed: 2011-12-02
- Granted: 2013-10-29
- Earliest claimed: 2011-12-02
- Assignees: Altera Corporation
- Applicants: Lip Kai Soh
- Inventors: Lip Kai Soh
- Web page: https://patentgrep.com/patent/US8571159B1

## CPC

- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H04L 7/0025: {interpolation of clock signal}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

## Claims

### Claim 1

A clock and data recovery circuit comprising:
a sampler circuit arranged to receive a data signal and a sampling clock and generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal;
a de-multiplexer circuit arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal;
a voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal;
a digital filter circuit arranged to filter the decimated feedback signal from the voting circuit and to output a filtered feedback signal;
a finite state machine circuit arranged to receive the filtered feedback signal and generate an interpolator control signal; and
a phase interpolator circuit arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal,
wherein the de-multiplexer circuit comprises higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

### Claim 2 (depends on 1)

The clock and data recovery circuit of claim 1, wherein the sampler and the phase interpolator circuits operate at a higher speed while the voting and finite state machine circuits operate at a slower speed.

### Claim 3 (depends on 1)

The clock and data recovery circuit of claim 1, wherein the feedback signal comprises an early signal indicating that the sampling clock is leading the data signal and a late signal indicating that the sampling clock is lagging the data signal.

### Claim 4 (depends on 3)

The clock and data recovery circuit of claim 3, wherein the de-multiplexer circuit includes a first sub-circuit to de-multiplex the early signal and a second sub-circuit to de-multiplex the late signal.

### Claim 5 (depends on 1)

The clock and data recovery circuit of claim 1, wherein the de-multiplexer circuit is programmable to a plurality of de-multiplexing settings.

### Claim 6 (depends on 5)

The clock and data recovery circuit of claim 5, wherein the voting circuit comprises a majority voting circuit with a plurality of programmable settings for at least one of the de-multiplexer settings.

### Claim 7 (depends on 1)

The clock and data recovery circuit of claim 1, wherein the digital filter is programmable to a plurality of filter settings.

### Claim 8

A method for clock and data recovery from a data signal, the method comprising:
generating a feedback signal which is responsive to a phase of a data signal relative to a sampling clock signal;
de-multiplexing the feedback signal to generate a de-multiplexed feedback signal;
decimating the de-multiplexed feedback signal to generate a decimated feedback signal;
filtering the decimated feedback signal to generate a filtered feedback signal;
generating an interpolator control signal using the filtered feedback signal and a finite state machine; and
generating the sampling clock by interpolation using a reference clock and the interpolator control signal,
wherein the de-multiplexing is performed by higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

### Claim 9 (depends on 8)

The method of claim 8, wherein the feedback signal and the sampling clock are generated by circuitry operating at a higher speed, while the decimated feedback signal, the filtered feedback signal, and interpolator control signal are generated by circuitry operating at a lower speed.

### Claim 10 (depends on 8)

The method of claim 8, wherein the feedback signal comprises an early signal indicating that the sampling clock is leading the data signal and a late signal indicating that the sampling clock is lagging the data signal.

### Claim 11 (depends on 10)

The method of claim 10, wherein the early and late signals are each de-multiplexed by a 1:N de-multiplexer, wherein N is programmable to one of a plurality of numbers.

### Claim 12 (depends on 11)

The method of claim 11, wherein the decimating is performed by a majority voting circuit which is programmable to one of a plurality of settings.

### Claim 13 (depends on 12)

The method of claim 12, wherein the filtering is performed by a digital filter circuit which is programmable to one of a plurality of settings.

### Claim 14

A receiver for a data link, the receiver comprising:
a buffer circuit arranged to receive a data signal and generate a buffered data signal; and
a programmable clock and data recovery circuit arranged to generate a sampling clock from the buffered data signal, the clock and data recovery circuit including
a sampler arranged to generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal,
a programmable de-multiplexer arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal, wherein the programmable de-multiplexer is configurable to a plurality of de-multiplexer settings,
a programmable voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal, wherein the voting circuit comprises a majority voting circuit with a plurality of programmable settings for at least one of the de-multiplexer settings,
a digital filter arranged to filter the decimated feedback signal and output a filtered feedback signal,
a finite state machine arranged to receive the filtered feedback signal and generate an interpolator control signal, and
a phase interpolator arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal.

### Claim 15 (depends on 14)

The receiver of claim 14, wherein the programmable de-multiplexer comprises higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

### Claim 16 (depends on 15)

The receiver circuit of claim 15, wherein the sampler and the phase interpolator operate at a higher speed while the voting circuit, digital filter, and finite state machine operate at a slower speed.