# US 8,571,158 B2 · Method and data transceiving system for generating reference clock signal

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,571,158 B2
- Document ID: US8571158B2
- Status: Granted
- Kind: B2
- Application number: 12/857,754
- Filed: 2010-08-17
- Published: 2011-12-22
- Granted: 2013-10-29
- Earliest claimed: 2010-06-22
- Assignees: Phison Electronics Corp.
- Applicants: An-Chung Chen; Wen-Lung Cheng; Wei-Yung Chen
- Inventors: An-Chung Chen; Wen-Lung Cheng; Wei-Yung Chen
- Web page: https://patentgrep.com/patent/US8571158B2

## CPC

- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.

## Claims

### Claim 1

A data transceiving system for generating a reference clock signal, comprising:
a voltage controlled oscillator, for generating the reference clock signal;
a phase lock loop (PLL) unit, coupled to the voltage controlled oscillator, for increasing a clock frequency of the reference clock signal to generate a PLL clock signal; and
a data receiver, coupled to the PLL unit and the voltage controlled oscillator, for receiving an input data stream and the PLL clock signal so as to output a voltage adjusting signal to the voltage controlled oscillator, wherein the data receiver comprises:
a frequency detector, for receiving the input data stream and comparing a clock frequency of the PLL clock signal with a base frequency of the clock signal of the input data stream, so as to generate a frequency adjusting signal;
a clock and data recovery circuit, for receiving the input data stream and the PLL clock signal, and transforming the input data stream into a retimed data stream by using the PLL clock signal as a reference clock;
a SOF decoder, for finding a start-of-frame (SOF) of each of a plurality of frames in the retimed data stream, so as to generate SOF signals; and
a frequency lock controller, for receiving the frequency adjusting signal and the PLL clock signal and accordingly generating the voltage adjusting signal, or receiving the SOF signals generated by the SOF decoder and the PLL clock signal, counting the SOF signals by using the PLL clock signal, and accordingly generating the voltage adjusting signal,
wherein the voltage controlled oscillator adjusts the clock frequency of the reference clock signal according to the voltage adjusting signal, so as to lock the clock frequency of the PLL clock signal generated by the PLL unit to the base frequency of the clock signal of the input data stream,
wherein when the SOF is not detected, the frequency lock controller receives the frequency adjusting signal and the clock signal and accordingly generates the voltage adjusting signal, so as to determine whether to increase or reduce the clock frequency of the reference clock signal, and when the SOF is detected by the SOF decoder, the frequency lock controller counts a number of the SOF of the plurality of frames in the retimed data stream, which is transformed from the input data stream, to determine whether to increase or reduce the clock frequency of the reference clock signal.

### Claim 2 (depends on 1)

The data transceiving system as claimed in claim 1, wherein the frequency detector comprises:
outputting a logic high signal when the base frequency of the clock signal of the input data stream is larger than the clock frequency of the PLL clock signal; and
outputting a logic low signal when the base frequency of the clock signal of the input data stream is smaller than the clock frequency of the PLL clock signal.

### Claim 3 (depends on 2)

The data transceiving system as claimed in claim 2, wherein the frequency lock controller increases a value of the voltage adjusting signal when receiving the logic high signal, so as to control the voltage controlled oscillator to increase the clock frequency of the reference clock signal, and reduces a value of the voltage adjusting signal when receiving the logic low signal, so as to control the voltage controlled oscillator to reduce the clock frequency of the reference clock signal.

### Claim 4 (depends on 1)

The data transceiving system as claimed in claim 1, wherein the frequency lock controller executes a plurality of steps, and the steps comprises:
comparing a count of the SOF signals with a standard value;
increasing a value of the voltage adjusting signal when the count is smaller than the standard value, so as to control the voltage controlled oscillator to increase the clock frequency of the reference clock signal; and
reducing a value of the voltage adjusting signal when the count is larger than the standard value, so as to control the voltage controlled oscillator to reduce the clock frequency of the reference clock signal.

### Claim 5 (depends on 1)

The data transceiving system as claimed in claim 1, wherein the voltage controlled oscillator increases or reduces the clock frequency of the reference clock signal by a frequency level according to the voltage adjusting signal.

### Claim 6 (depends on 5)

The data transceiving system as claimed in claim 5, wherein the frequency level is a product of a frequency gain and a voltage variation of the voltage controlled oscillator.

### Claim 7 (depends on 6)

The data transceiving system as claimed in claim 6, further comprising:
a digital-to-analog converter, disposed between the voltage controlled oscillator and the data receiver, for transforming the voltage adjusting signal outputted by the data receiver into the voltage variation, so as to adjust the clock frequency of the reference clock signal generated by the voltage controlled oscillator.

### Claim 8 (depends on 1)

The data transceiving system as claimed in claim 1, further comprising:
a data transmitter, coupled to the PLL unit, for receiving an output data stream and the PLL clock signal, and transmitting the output data stream according to the PLL clock signal.

### Claim 9

A method for generating a reference clock signal, comprising:
generating the reference clock signal by using a voltage controlled oscillator;
increasing a clock frequency of the reference clock signal to generate a PLL clock signal;
comparing the PLL clock signal with a clock signal of an input data stream, and accordingly outputting a voltage adjusting signal; and
adjusting the clock frequency of the reference clock signal generated by the voltage controlled oscillator according to the voltage adjusting signal, so as to lock the clock frequency of the generated PLL clock signal to a base frequency of the clock signal of the input data stream, wherein the step of comparing the PLL clock signal with the clock signal of the input data stream and accordingly outputting the voltage adjusting signal comprises:
receiving the input data stream and comparing the clock frequency of the PLL clock signal with the base frequency of the clock signal of the input data stream, so as to generate a frequency adjusting signal;
receiving the input data stream and the PLL clock signal, and transforming the input data stream into a retimed data stream by using the PLL clock signal as a reference clock;
finding a start-of-frame (SOF) of each of a plurality of frames in the retimed data stream, so as to generate SOF signals; and
receiving the frequency adjusting signal and the PLL clock signal and accordingly generating the voltage adjusting signal, or receiving the SOF signals and the PLL clock signal, counting the SOF signals by using the PLL clock signal, and accordingly generating the voltage adjusting signal,
wherein when the SOF is not detected, the frequency adjusting signal and the PLL clock signal are received to generate the voltage adjusting signal, so as to determine whether to increase or reduce the clock frequency of the reference clock signal, and when the SOF is detected, a number of the SOF of the plurality of frames in the retimed data stream, which is transformed from the input data stream, is counted to determine whether to increase or reduce the clock frequency of the reference clock signal.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the step of comparing the clock frequency of the PLL clock signal with the base frequency of the clock signal of the input data stream, so as to generate the voltage adjusting signal comprises:
outputting a logic high signal when the base frequency of the clock signal of the input data stream is larger than the clock frequency of the PLL clock signal; and
outputting a logic low signal when the base frequency of the clock signal of the input data stream is smaller than the clock frequency of the PLL clock signal.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the step of receiving the frequency adjusting signal and the PLL clock signal and accordingly generating the voltage adjusting signal comprises:
increasing a value of the voltage adjusting signal when receiving the logic high signal, so as to control the voltage controlled oscillator to increase the clock frequency of the reference clock signal; and
reducing a value of the voltage adjusting signal when receiving the logic low signal, so as to control the voltage controlled oscillator to reduce the clock frequency of the reference clock signal.

### Claim 12 (depends on 9)

The method as claimed in claim 9, wherein the step of counting the SOF signals by using the PLL clock signal, and accordingly generating the voltage adjusting signal comprises:
comparing a count of the SOF signals with a standard value;
increasing a value of the voltage adjusting signal when the count is smaller than the standard value, so as to control the voltage controlled oscillator to increase the clock frequency of the reference clock signal; and
reducing a value of the voltage adjusting signal when the count is larger than the standard value, so as to control the voltage controlled oscillator to reduce the clock frequency of the reference clock signal.

### Claim 13 (depends on 9)

The method as claimed in claim 9, wherein the step of adjusting the clock frequency of the reference clock signal generated by the voltage controlled oscillator according to the voltage adjusting signal comprises:
increasing or reducing the clock frequency of the reference clock signal generated by the voltage controlled oscillator by a frequency level according to the voltage adjusting signal.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the frequency level is a product of a frequency gain and a voltage variation of the voltage controlled oscillator.

### Claim 15 (depends on 14)

The method as claimed in claim 14, wherein after the step of comparing the PLL clock signal with the clock signal of the input data stream, and accordingly outputting a voltage adjusting signal, the method further comprising:
transforming the voltage adjusting signal into the voltage variation, so as to adjust the clock frequency of the reference clock signal generated by the voltage controlled oscillator.

### Claim 16 (depends on 14)

The method as claimed in claim 14, wherein after the step of adjusting the clock frequency of the reference clock signal generated by the voltage controlled oscillator according to the voltage adjusting signal, so as to lock the clock frequency of the generated PLL clock signal to a base frequency of the clock signal of the input data stream, the method further comprising:
transmitting an output data stream according to the PLL clock signal.