# US 8,571,119 B2 · Software defined radio for modulation and demodulation of multiple communication standards

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- Number: US 8,571,119 B2
- Document ID: US8571119B2
- Status: Granted
- Kind: B2
- Application number: 13/435,326
- Filed: 2012-03-30
- Published: 2012-10-04
- Granted: 2013-10-29
- Earliest claimed: 2011-04-01
- Assignees: Saankhya Labs Pvt. Ltd.
- Applicants: Parag Naik; Anindya Saha; Hemant Mallapur; Sunil Hr; Gururaj Padaki
- Inventors: Parag Naik; Anindya Saha; Hemant Mallapur; Sunil Hr; Gururaj Padaki
- Web page: https://patentgrep.com/patent/US8571119B2

## CPC

- H04B 1/0007: {wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/2936: {comprising an outer Reed-Solomon code and an inner convolutional code}
- H03M 13/6522: {Intended application, e.g. transmission or communication standard}
- H04H 40/18: Arrangements characterised by circuits or components specially adapted for receiving
- H04N 5/455: Demodulation-circuits
- H04N 5/46: for receiving on more than one standard at will (deflecting circuits of multi-standard receivers H04N3/27)
- H04N 21/2383: Channel coding {or modulation} of digital bit-stream, e.g. QPSK modulation (arrangements for detecting or preventing errors in the information received by adapting the channel coding H04L1/0009; analogue front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002)
- H04N 21/4382: {Demodulation or channel decoding, e.g. QPSK demodulation (analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002)}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/27: using interleaving techniques
- H04B: TRANSMISSION
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04H: BROADCAST COMMUNICATION (multiplex communication H04J; pictorial communication aspects of broadcast systems H04N)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

## Claims

### Claim 1

A Software Defined Radio (SDR) subsystem capable of supporting multiple communication standards, for modulation and demodulation of an input signal, said SDR subsystem comprising:
a Signal Conditioning Cluster (SCC) unit;
a Signal Processing Cluster (SPC) unit; and
a Channel Codec Cluster (CCC) unit that performs a channel encoding and a channel decoding;
wherein said SCC unit (i) receives a baseband signal from said SPC unit and produces a digital Intermediate Frequency (IF) signal for said modulation, and (ii) receives an IF signal from a tuner and produces a complex baseband signal for said demodulation; wherein said SPC unit (i) receives encoded bits from said CCC unit and produces said baseband signal for said modulation, and (ii) receives said complex baseband signal from said SCC unit and produces decision bits for said demodulation; wherein said CCC unit (i) receives said input signal and produces said encoded bits for said modulation, and (ii) receives said decision bits from said SPC unit and produces a decoded data for said demodulation.

### Claim 2 (depends on 1)

The SDR subsystem of claim 1, wherein said SCC unit (i) receives said baseband signal from said SPC unit and produces said digital Intermediate Frequency (IF) signal based on a first communication standard for a trans-modulation, and (ii) receives said IF signal from said tuner and produces said complex baseband signal based on a second communication standard for said trans-modulation.

### Claim 3 (depends on 2)

The SDR subsystem of claim 2, wherein said SPC unit (i) receives said encoded bits from said CCC unit and produces said baseband signal based on said first communication standard for said trans-modulation, and (ii) receives said complex baseband signal from said SCC unit and produces said decision bits based on said second communication standard for said trans-modulation.

### Claim 4 (depends on 1)

The SDR subsystem of claim 1, wherein said multiple communication standards comprise analog and digital communication standards, wherein said SCC unit further comprises: a Digital Front End (DFE) unit that comprises: a Numerically Controlled Oscillator (NCO) that operates at a sample-rate frequency and that performs a digital down-conversion of said IF signal into said complex baseband signal; a plurality of Signal Conditioning (SCON) CPUs adapted for a sample based signal processing that (i) perform a pulse shaping of said baseband signal from said SPC unit for said modulation, and (ii) perform a Finite Impulse Response (FIR) filtering, an Infinite Impulse Response (IIR) filtering, an interpolation, and a sample rate conversion filtering on said complex baseband signal from said NCO for said demodulation; and a memory sub system that comprises: a store-and-forward buffer or a cut-through buffer for storing said complex baseband signal or said baseband signal; and a Direct Memory Access (DMA) unit that extracts data that corresponds to said complex baseband signal or said baseband signal from said store-and-forward buffer or said cut-through buffer based on a programmed threshold.

### Claim 5 (depends on 1)

The SDR subsystem of claim 1, wherein said SPC unit comprises: a plurality of Signal Processing (SPROC) CPUs adapted for a block based signal processing that (i) perform a modulation, a framing and a mapping on said encoded bits from said CCC unit to produce said baseband signal for said modulation of said input signal, and (ii) perform a demodulation, a channel estimation, a channel correction, and de-mapping of symbols on said complex baseband signal received from said SCC unit to produce said decision bits for said demodulation of said input signal; a Least Mean Squares (LMS) coprocessor coupled to said plurality of SPROC CPUs, wherein said LMS coprocessor performs an adaptive feedback and feed-forward FIR filtering, a coefficient or tap adaptation, and a high speed FIR filtering operation on multiple streams; and a memory subsystem that comprises: an Inter-Cluster Buffer (ICB); a Shared Memory Subsystem (SHM) that is connected across said plurality of SPROC CPUs wherein said SHM is used as a buffer for storing and exchanging of computed results between said plurality of SPROC CPUs; and a DMA unit that processes a transfer of a processed data to said CCC unit.

### Claim 6 (depends on 5)

The SDR subsystem of claim 5, wherein said plurality of SPROC CPUs comprises: a complex arithmetic slot that performs at least one of real and complex arithmetic operations, wherein said operations include N-way Single Instruction Multiple Data (SIMD) operations, wherein said complex arithmetic slot supports Fast Fourier Transform (FFT) butterfly operations; and a cordic slot that generates (i) sine and cosine values and (ii) magnitude and phases of complex signals, wherein said cordic slot is coupled to said LMS coprocessor to perform cycle efficient read and write operations during an equalizer operation, wherein said cordic slot further performs N-way arithmetic, logic and extract operations.

### Claim 7 (depends on 1)

The SDR subsystem of claim 1, wherein said CCC unit (i) receives said input signal and performs at least one of a viterbi encoding, a Reed Solomon (RS) encoding, and a Low-Density Parity-Check (LDPC) to produce said encoded bits for said modulation, and (ii) receives said decision bits from said SPC unit and performs at least one of a viterbi decoding, a Reed Solomon (RS) decoding, and a Low-Density Parity-Check (LDPC) to produce said decoded data for said demodulation.

### Claim 8

A method for demodulating an input signal in software defined radio (SDR) subsystem that is capable of supporting multiple communication standards, said method comprising:
receiving from a tuner one of a zero Intermediate Frequency (IF) signal, a low IF signal, and a standard IF signal;
down converting one of said low IF signal, and said standard IF signal into a down converted IF signal;
performing a FIR filtering, an IIR filtering, an interpolation and a sample rate conversion filtering on said down converted IF signal to produce a filtered complex baseband signal using a Signal Conditioning CPU (SCON CPU) adapted for a sample based signal processing;
performing a demodulation, a channel estimation, a channel correction, and a de-mapping on said filtered complex baseband signal based on said multiple communication standards to obtain decision bits using a Signal Processing CPU (SPROC CPU) adapted for a block based signal processing; and
performing at least one of a Viterbi decoding, a Reed Solomon (RS) decoding, and a Low-Density Parity-Check (LDPC) decoding on said decision bits to obtain decoded data.

### Claim 9 (depends on 8)

The method of claim 8, further comprising: performing loading and storing of said complex baseband signal, using a load-store slot of said Signal Conditioning CPU (SCON CPU), to enable filtering operation; performing, using said filter slot of said SCON CPU, said FIR filtering, said IIR filtering, said interpolation and said sample rate conversion filtering on a complex baseband signal obtained from said load-store slot; and performing, using an arithmetic slot of said SCON CPU, arithmetic operations required for filtering operation.

### Claim 10 (depends on 8)

The method of claim 8 further comprising performing, using a complex arithmetic slot and a cordic slot of said Signal Processing CPU (SPROC CPU), said demodulation, said channel estimation, said channel correction, and said de-mapping on said filtered complex baseband signal.

### Claim 11

A method for modulating an input signal in a software defined radio (SDR) subsystem that is capable of supporting multiple communication standards, said method comprising:
performing at least one of a Viterbi encoding, a Reed Solomon (RS) encoding, convolution encoding and a Low-Density Parity-Check (LDPC) encoding on said input signal to produce encoded bits;
performing a modulation, a framing, and a mapping on said encoded bits based on said multiple communication standards to obtain baseband signals using a Signal Processing CPU (SPROC CPU) adapted for a block based signal processing;
performing an up-conversion and a pulse shaping of said baseband signals to produce a digital IF signal using a Signal Conditioning CPU (SCON CPU) adapted for a sample based signal processing;
converting said digital IF signal into an analog signal; and
performing, using a complex arithmetic slot and a cordic slot of said Signal Processing CPU (SPROC CPU), said modulation, said framing and said mapping on said encoded bits.

### Claim 12 (depends on 11)

The method of claim 11 further comprising performing, using a load-store slot, a filter slot, and an arithmetic slot of said Signal Conditioning CPU (SCON CPU), said up-conversion and said pulse shaping of said baseband signals.