# US 8,570,828 B2 · Memory programming using variable data width

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- Number: US 8,570,828 B2
- Document ID: US8570828B2
- Status: Granted
- Kind: B2
- Application number: 13/008,522
- Filed: 2011-01-18
- Published: 2011-10-13
- Granted: 2013-10-29
- Earliest claimed: 2010-04-12
- Assignees: Mosaid Technologies Incorporated
- Applicants: Hong Beom Pyeon
- Inventors: Hong Beom Pyeon
- Web page: https://patentgrep.com/patent/US8570828B2

## CPC

- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0085: {Write a page or sector of information simultaneously, e.g. a complete row or word line}
- G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

## Claims

### Claim 1

A method of programming a memory comprising:
determining a programming number of bits in a word to be programmed into a memory wherein each bit to be programmed is in a particular logical state, the determining comprising asynchronously adding;
partitioning the word into two or more sub-words when the programming number exceeds a maximum number; and
sequentially writing each of the sub-words into the memory.

### Claim 2 (depends on 1)

The method of claim 1 wherein partitioning the word further comprises dividing the word into a binary multiple of sub-words, each sub-word including a same number of bits as each other sub-word.

### Claim 3 (depends on 1)

The method of claim 1 wherein the particular logical state is a RESET state.

### Claim 4

A variable data width system comprising:
an adder configured to determine a programming number of bits in a word to be programmed into a memory wherein each bit to be programmed is in a particular logical state, the adder comprising a plurality of asynchronous adders;
a partitioning block configured to divide the word into two or more sub-words when the programming number exceeds a maximum number, each sub-word including a same number of bits as each other sub-word; and
a switch in communication with the partitioning block, the switch being configured to sequentially provide one or more write pulses, each write pulse enabling a separate communication path between the memory and one of the word and the sub-words.

### Claim 5 (depends on 4)

The system of claim 4 further comprising a register holding the programming number until a completion of a subsequent write operation.

### Claim 6 (depends on 4)

The system of claim 4 further comprising a register in communication with the partitioning block and adapted to store the maximum number therein.

### Claim 7 (depends on 6)

The system of claim 6 further comprising a write driver enabler in communication with the register, the write driver enabler selecting a driver strength in response to the maximum number.

### Claim 8 (depends on 6)

The system of claim 6 further comprising a write driver enabler in communication with the register, the write driver enabler selecting a one or more drivers in response to the maximum number, all of the one or more drivers having a common charge pump input and a common driver output.

### Claim 9 (depends on 4)

The system of claim 4 wherein the partitioning block comprises a plurality of combinatorial logic gates enabling a full-width signal when the programming number is not greater than the maximum number.

### Claim 10 (depends on 4)

The system of claim 4 wherein the partitioning block comprises a plurality of combinatorial logic gates enabling a half-width signal when the programming number is greater than the maximum number and the maximum number is equal to one-half of the number of bits of the word.

### Claim 11 (depends on 4)

The system of claim 4 wherein the partitioning block comprises a plurality of combinatorial logic gates enabling a quarter-width signal when the programming number is greater than the maximum number and the maximum number is equal to one-quarter of the number of bits of the word.

### Claim 12 (depends on 4)

The system of claim 4 wherein the partitioning block comprises a plurality of combinatorial logic gates enabling an eighth-width signal when the programming number is greater than the maximum number and the maximum number is equal to one-eighth of the number of bits of the word.

### Claim 13 (depends on 4)

The system of claim 4 wherein the switch generates one write pulse in response to a full-width signal, the write pulse enabling the separate communication path between the word and the memory.

### Claim 14 (depends on 4)

The system of claim 4 wherein the switch generates two write pulses in response to a half-width signal, each write pulse enabling the separate communication path between a sub-word and the memory, each sub-word including half of the number of bits of the word.

### Claim 15 (depends on 4)

The system of claim 4 wherein the switch generates four write pulses in response to a quarter-width signal, each write pulse enabling the separate communication path between a sub-word and the memory, each sub-word including one-quarter of the number of bits of the word.

### Claim 16 (depends on 4)

The system of claim 4 wherein the switch generates eight write pulses in response to a eighth signal, each write pulse enabling the separate communication path between a sub-word and the memory, each sub-word including one-eighth of the number of bits of the word.

### Claim 17

A memory system comprising:
a memory including a plurality of bits arranged as one or more words, each bit in each word being capable of being programmed either to a particular logical state or to another logical state; and
a variable data width controller in communication with the memory, the variable data width controller comprising:
an adder configured to determine a programming number of bits in a word to be programmed into a memory wherein each bit to be programmed is in the particular logical state, the adder comprising a plurality of asynchronous adders;
a partitioning block configured to divide the word into two or more sub-words when the programming number exceeds a maximum number; and
a switch in communication with the partitioning block, the switch being configured to sequentially provide one or more write pulses, each write pulse enabling a separate communication path between the memory and one of the word and the sub-words.

### Claim 18 (depends on 17)

The memory system of claim 17 wherein the memory is a phase change memory and the particular logical state represents an amorphous state.

### Claim 19 (depends on 17)

The memory system of claim 17 wherein the memory is a magneto-resistive random access memory.