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US 8,570,827 B2Granted
Physical organization of memory to reduce power consumption
AssigneeApple Inc.
InventorsSteven C. Sullivan, Abhijeet R. Tanpure, William V. Miller, Ben D. Jarrett
Life of this patent
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Abstract
Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.
Claims20
A memory, comprising:
- a first array including a plurality of first wordline drivers;
- and
- a second array including a plurality of second wordline drivers;
- wherein the plurality of first wordline drivers is configured to receive a first enable signal, and the plurality of second wordline drivers is configured to receive a second enable signal,
- wherein the first and the second enable signals are derived from an address bit of an address used to access the memory, and
- wherein the first and the second enable signals are active mutually exclusive.
3 more elements
An apparatus, comprising:
- a first wordline decoder for a plurality of first wordline drivers and a second wordline decoder for a plurality of second wordline drivers, wherein each wordline decoder is configured to receive a respective signal to activate, wherein the respective signals are active mutually exclusive;
- a plurality of first cache array latches coupled to the plurality of first wordline drivers, wherein each first cache array latch is configured to output a first cache line of data;
- and
- a plurality of second cache array latches coupled to the plurality of second wordline drivers, wherein each second cache array latch is configured to output a second cache line of data, wherein each of the plurality of first cache array latches is coupled to a corresponding one of the plurality of second cache array latches,
- wherein an address bit of an address for accessing the first and second cache lines of data is usable to select whether to enable the first wordline decoder signal or to enable the second wordline decoder signal.
2 more elements
A system, comprising:
- a memory;
- and
- one or more processors coupled to the memory, wherein at least one of the one or more processors includes a cache memory;
- wherein the cache memory comprises:
- a first array configured to output a first cache line of data, wherein the first array includes a plurality of first wordline drivers, and
- a second array configured to output a second cache line of data, wherein the second array includes a plurality of second wordline drivers, wherein an output of the first array is coupled to an output of the second array,
- wherein the plurality of first wordline drivers is configured to be enabled by a first enable signal, and wherein the plurality of second wordline drivers is configured to be enabled by a second enable signal,
- wherein the first and the second enable signals are derived from a single address bit of an address used to access the cache memory, and
- wherein the first and the second enable signals are active mutually exclusive.
6 more elements
A method, comprising:
- before a start of a clock cycle:
- a first array and second array of a memory receiving a portion of an address, wherein the first array includes a plurality of first wordline drivers and wherein the second array includes a plurality of second wordline drivers;
- the plurality of first wordline drivers receiving an asserted first wordline enable signal without the plurality of second wordline drivers receiving an asserted second wordline enable signal, wherein the first and second wordline enable signals are derived from an address bit of the address that is separate from the portion of the address received by the first and second arrays, and wherein the first and second wordline enable signals are active mutually exclusive;
- and
- the plurality of first wordline drivers activating in response to the asserted first wordline enable signal and the plurality of second wordline drivers deactivating in response to not receiving the asserted second wordline enable signal.
2 more elements
Dependencies are inferred from the claim text.