US 8,570,826 B2 · Memory device having data paths facilitating array/contact consolidation and/or swapping

Abstract

Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus.

Claims21

Dependent claims

An apparatus comprising:

a plurality of memory arrays comprising a first memory array and a second memory array adjacent to each other, the first memory array comprising a first memory cell and a second memory cell, and the second memory array comprising a third memory cell;
a first contact configured for input and/or output of data;
a second contact configured for input and/or output of data, the first memory array and the second memory array being interposed between the first contact and the second contact;
a plurality of master data lines comprising a first master data line and a second master data line, the first master data line being electrically connectable to the first contact, and the second master data line being electrically connectable to the second contact;
a first local data line configured to selectively carry data in a first path between the first memory cell and the first master data line, and to selectively carry data in a third path between the third memory cell and the first master data line;
and
a second local data line configured to selectively carry data in a second path between the second memory cell and the second master data line.

4 more elements

An apparatus comprising:

a plurality of memory arrays comprising a first memory array and a second memory array adjacent to each other, wherein the first memory array comprises a plurality of banks and a midgap between two of the plurality of banks;
a plurality of master data lines comprising a first master data line and a second master data line;
a plurality of local data lines comprising a first local data line and a second local data line, the first local data line extending over at least a portion of the first memory array and at least a portion of the second memory array, the first local data line being electrically connectable to the first master data line, the second local data line extending over at least a portion of the first memory array and at least a portion of the second memory array, and the second local data line being electrically connectable to the second master data line;
and
a midgap switch configured to selectively electrically couple a midgap line in the midgap of the first memory array to the first local data line, wherein a number of local data lines of the plurality of local data lines electrically coupled to the midgap switch is greater than a number of midgap lines electrically coupled to the midgap switch.

2 more elements

Dependencies are inferred from the claim text.

Memory device having data paths facilitating array/contact consolidation and/or swapping

Life of this patent

Memory device having data paths facilitating array/contact consolidation and/or swapping

Life of this patent

Abstract

Claims21