Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation

A memory comprising:

• a first storage array configured to provide first data on a first plurality of bit lines;
• a second storage array configured to provide second data on a second plurality of bit lines;
• a input/output (I/O) unit configured to output via a plurality of data output signal paths, the data received from the first storage array and the second storage array;
• a first isolation unit coupled to provide a data path between the first plurality of bit lines and the I/O unit when the first storage array is operating in a normal operational mode;
• a second isolation unit coupled to provide a data path between the second plurality of bit lines and the I/O unit when the second storage array is operating in the normal operational mode;
• wherein in response to the first storage array being placed in a low-voltage operational mode, the first isolation unit is configured to isolate the first plurality of bit lines from the I/O unit.

An integrated circuit comprising:

• a memory;
• an unswitched power rail configured to provide power to an unswitched voltage domain while applied to the integrated circuit;
• and
• a plurality of power gating circuits coupled to the unswitched power rail and configured to provide a plurality of switched voltage domains;
• wherein the memory includes:
• a plurality of storage arrays each coupled to a respective switched voltage domain and configured to provide data on a respective plurality of bit lines;
• a input/output (I/O) unit coupled to a respective switched voltage domain and configured to output via a plurality of data output signal paths, the data received from the plurality of storage arrays;
• a plurality of isolation units, each coupled to the unswitched voltage domain and configured to provide a data path between the respective plurality of bit lines of a corresponding respective one of the plurality of storage arrays and the I/O unit when the corresponding respective storage array is operating in a normal operational mode;
• wherein in response to a given storage array of the plurality of storage arrays being placed in a low-voltage operational mode, the corresponding respective isolation unit is configured to isolate the respective plurality of bit lines from the I/O unit.

A mobile communication device comprising:

• a memory;
• and
• a processor coupled to the memory, wherein the processor includes an embedded memory including:
• a plurality of storage arrays each configured to provide data on a respective plurality of bit lines;
• a input/output (I/O) unit configured to output via a plurality of data output signal paths, the data received from the plurality of storage arrays;
• a plurality of isolation units, wherein each isolation unit is coupled to provide a data path between the respective plurality of bit lines of a corresponding respective one of the plurality of storage arrays and the I/O unit when the corresponding respective storage array is operating in a normal operational mode;
• wherein in response to a given storage array of the plurality of storage arrays being placed in a low-voltage operational mode, the corresponding respective isolation unit is configured to isolate the respective plurality of bit lines from the I/O unit.