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US 8,570,823 B2Granted
Sense amplifier with low sensing margin and high device variation tolerance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Huei Chen, Hsien-Yu Pan, Shao-Yu Chou
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Abstract
In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.
Claims22
A sense amplifier comprising:
- a pair of data lines comprising a first data line and a second data line;
- a first pair of transistors of a predetermined type, the first pair of transistors comprising a first transistor and a second transistor, a gate terminal of the first transistor coupled with a drain terminal of the second transistor, and a gate terminal of the second transistor coupled with a drain terminal of the first transistor;
- a pair of nodes comprising a first node corresponding to the drain terminal of the first transistor and a second node corresponding to the drain terminal of the second transistor, and the pair of nodes arranged for providing read data for the sense amplifier;
- a second pair of transistors of the predetermined type, each of the second pair of transistors having a drain terminal coupled to a corresponding source terminal of the first pair of transistors and having a gate directly coupled to a corresponding one of the pair of data lines;
- and
- a pair of transferring devices comprising a first transferring device coupled between the first data line and the first node and a second transferring device coupled between the second data line and the second node;
- wherein in a read cycle, the first transferring device is configured to transfer data on the first data line directly to the first node;
- and the second transferring device is configured to transfer data on the second data line directly to the second node.
5 more elements
A sense amplifier comprising:
- a cross latch comprising a first transistor of a predetermined type, a second transistor of the predetermined type, and a first node and a second node from which data is read, the first node being at a drain terminal of the first transistor, and the second node being at a drain terminal of the second transistor;
- a first transferring device having a first terminal coupled to the first node and a second terminal coupled to a first data line;
- a second transferring device having a first terminal coupled to the second node and a second terminal coupled to a second data line;
- a third transistor of the predetermined type having a drain terminal coupled to a source terminal of the first transistor and a gate terminal directly coupled to the second data line;
- a fourth transistor of the predetermined type having a drain terminal coupled to a source terminal of the second transistor and a gate terminal directly coupled to the first data line;
- and
- a control signal configured to control the first transferring device, the second transferring device, and the cross latch.
4 more elements
A method comprising:
- in a read cycle related to a sense amplifier,
- turning off a cross latch corresponding to a first node and a second node of the sense amplifier, the cross latch comprising a first transistor of a predetermined type and a second transistor of the predetermined type, the first node being at a drain terminal of the first transistor, and the second node being at a drain terminal of the second transistor;
- turning on a first transferring device to electrically couple a first data line to the first node;
- turning on a second transferring device to electrically couple a second data line to a second node;
- charging, using a charge circuit, the first data line and the second data line;
- charging the first node and the second node using the charge circuit, the first transferring device and the second transferring device;
- transferring a differential signal corresponding to data from a bit cell to the first data line, the second data line, and gate terminals of a third transistor and a fourth transistor of the predetermined type, the third transistor having a drain terminal coupled to a source terminal of the first transistor and a gate terminal directly coupled to the second data line, and the fourth transistor having a drain terminal coupled to a source terminal of the second transistor and a gate terminal directly coupled to the first data line;
- and
- after one of the first and second nodes is discharged responsive to the differential signal, performing operations comprising:
- turning on the cross latch;
- turning off the first transferring device;
- and
- turning off the second transferring device.
10 more elements
Dependencies are inferred from the claim text.