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US 8,570,821 B2Granted
Semiconductor memory device and method for repairing the same
AssigneeSK hynix Inc.
InventorsSun Young Hwang, Sang Il Park
Life of this patent
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Abstract
A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.
Claims17
A semiconductor memory device comprising:
- a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines;
- and
- a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses,
- wherein the latch address generation unit generates the first and second latch addresses in response to a failure occurrence signal, which is asserted when at least one of the memory cells coupled to the sub word lines is faulty, and a test mode signal, which is asserted when a compression parallel test is performed.
1 more element
A method for repairing a semiconductor memory device, comprising:
- generating a first latch pulse signal in response to a failure occurrence signal, which is asserted when at least one of memory cells coupled to a first sub word line is faulty, and a test mode signal, which is asserted when a compression parallel test is performed;
- latching a row address to generate a first latch address in response to the first latch pulse signal;
- comparing the first latch address with the row address to generate a comparison signal when at least one of memory cells coupled to a second sub word line is faulty;
- and
- latching the row address to generate a second latch address in response to the comparison signal, wherein the first and second latch addresses select different main word lines.
2 more elements
Dependencies are inferred from the claim text.