# US 8,570,818 B2 · Address multiplexing in pseudo-dual port memory

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- Number: US 8,570,818 B2
- Document ID: US8570818B2
- Status: Granted
- Kind: B2
- Application number: 12/814,682
- Filed: 2010-06-14
- Published: 2011-03-03
- Granted: 2013-10-29
- Earliest claimed: 2008-03-13
- Assignees: QUALCOMM Incorporated
- Applicants: Chang Ho Jung; Cheng Zhong
- Inventors: Chang Ho Jung; Cheng Zhong
- Web page: https://patentgrep.com/patent/US8570818B2

## CPC

- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

## Claims

### Claim 1

A pseudo dual port memory address multiplexing system comprising:
a read port address latch operable to hold a read address in response to an external signal;
a write port address latch operable to hold a write address in response to the external signal;
a control circuit that controls read/write memory access based upon monitoring of a first memory operation by sending a switch signal; and
a multiplexer that switches between a held read address and a held write address in response to the switch signal from the control circuit.

### Claim 2 (depends on 1)

The pseudo-dual port memory address multiplexing system of claim 1, in which the first memory operation is a memory read operation.

### Claim 3 (depends on 2)

The pseudo-dual port memory address multiplexing system of claim 2, in which the read port address latch releases after the read operation.

### Claim 4 (depends on 3)

The pseudo-dual port memory address multiplexing system of claim 3, in which the write address latch remains latched after the read operation.

### Claim 5 (depends on 4)

The pseudo-dual port memory address multiplexing system of claim 4, in which the write port address releases after a write operation.

### Claim 6 (depends on 1)

The pseudo-dual port memory address multiplexing system according to claim 1, in which the control circuit comprises a self time delay circuit that creates a self timing delay, the control circuit asserting an internal clock signal after the self timing delay to start a second memory operation.

### Claim 7 (depends on 2)

The pseudo-dual port memory address multiplexing system according to claim 2, in which the control circuit comprises a self time tracking circuit that initiates generation of the switch signal in response to detected completion of said read operation.

### Claim 8 (depends on 7)

The pseudo-dual port memory address multiplexing system according to claim 7, wherein the detected completion is based upon monitoring of a dummy bit.

### Claim 9 (depends on 1)

The pseudo-dual port memory address multiplexing system according to claim 1, wherein said control circuit is operative to identify read/write, read only, and write only modes of operation.

### Claim 10 (depends on 2)

The pseudo-dual port memory address multiplexing system according to claim 2, in which the control circuit advances a timing of a write operation in response to an absence of a read request.

### Claim 11 (depends on 1)

The pseudo-dual port memory address multiplexing system according to claim 1, in which the first memory operation is a write operation.

### Claim 12 (depends on 2)

The pseudo-dual port memory address multiplexing system according to claim 2, wherein said multiplexer is operable to maintain a default condition whereby said read address is transmitted to said memory address unit.

### Claim 13 (depends on 2)

The pseudo-dual port memory address multiplexing system according to claim 2, further comprising a pre-decoder that receives the held write address after the read operation is at least substantially complete.

### Claim 14 (depends on 13)

The pseudo-dual port memory address multiplexing system according to claim 13, further comprising a gate that receives the write address from the pre-decoder before receiving a second assertion of an internal clock signal, a first assertion of the internal clock signal being responsive to the external signal.

### Claim 15 (depends on 1)

The pseudo-dual port memory addressing system of claim 1, wherein the external signal is comprised of one of the following:
the clock signal and a read signal and a write signal; or
the clock signal and a write signal; or a clock signal and a read signal.

### Claim 16 (depends on 1)

The pseudo dual port memory address multiplexing system of claim 1, integrated in at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

### Claim 17

A pseudo dual port memory address multiplexing method comprising:
holding a read address in a memory in response to an external signal;
holding a write address in response to the external signal;
controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal; and
switching between a held read address and a held write address in response to the switch signal.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising:
generating a self timing delay; and
asserting an internal clock signal after the self timing delay to start a second memory operation.

### Claim 19 (depends on 17)

The method according to claim 17, further comprising: identifying read/write, read only, and write only modes of operation.

### Claim 20 (depends on 17)

The method according to claim 17, in which the first memory operation is a write operation.

### Claim 21 (depends on 17)

The method of claim 17, in which the external signal is comprised of:
a clock signal and a read signal and a write signal; or
the clock signal and the write signal; or
the clock signal and the read signal.

### Claim 22 (depends on 17)

The method of claim 17, in which the first memory operation is a memory read operation.

### Claim 23 (depends on 22)

The method of claim 22, further comprising releasing a read port address latch after the read operation.

### Claim 24 (depends on 23)

The method of claim 23, further comprising keeping a write address latch latched after the read operation.

### Claim 25 (depends on 24)

The method of claim 24, in which the write port address releases after a write operation.

### Claim 26 (depends on 22)

The method according to claim 22, further comprising:
detecting a completion of said read operation; and
initiating generation of the switch signal in response to the completion of said read operation.

### Claim 27 (depends on 26)

The method according to claim 26, in which the detecting a completion is based upon monitoring of a dummy bit.

### Claim 28 (depends on 22)

The method according to claim 22, further comprising: advancing a timing of a write operation in response to an absence of a read request.

### Claim 29 (depends on 17)

The method of claim 17, further comprising integrating the memory into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

### Claim 30

A pseudo dual port memory address multiplexing method comprising the steps of:
holding a read address in a memory in response to an external signal;
holding a write address in response to the external signal;
controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal; and
switching between a held read address and a held write address in response to the switch signal.

### Claim 31 (depends on 30)

The method of claim 30, further comprising the step of integrating the memory into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

### Claim 32

A pseudo dual port memory address multiplexing apparatus comprising:
means for holding a read address in a memory in response to an external signal;
means for holding a write address in the memory in response to the external signal;
means for controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal; and
means for switching between a held read address and a held write address in response to the switch signal.

### Claim 33 (depends on 32)

The method according to claim 32, further comprising:
means for generating a self timing delay; and
means for asserting an internal clock signal after the self timing delay to start a second memory operation.

### Claim 34

The apparatus according to claim. 32, further comprising means for identifying read/write, read only, and write only modes of operation.

### Claim 35 (depends on 32)

The apparatus according to claim 32, in which the first memory operation is a write operation.

### Claim 36 (depends on 35)

The apparatus of claim 35, integrated in at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

### Claim 37 (depends on 32)

The apparatus of claim 32, in which the first memory operation is a memory read operation.

### Claim 38 (depends on 37)

The apparatus of claim 37, further comprising: means for releasing the read port address latch after the read operation.

### Claim 39 (depends on 38)

The apparatus of claim 38, further comprising: means for keeping the write address latch latched after the read operation.