Charge pump circuit using low voltage transistors

A memory device comprising:

• an array of memory cells and a charge pump circuit coupled thereto, said charge pump circuit comprising a plurality of charge pump stages cascaded to one another, each charge pump stage comprising
• a first pump capacitor coupled to a first internal node and configured to receive a first high voltage phase signal, and a second pump capacitor coupled to a second internal node and configured to receive a second high voltage phase signal, complementary with respect to the first high voltage phase signal,
• a first transfer transistor coupled between the first internal node and an intermediate node between said charge pump stage and a subsequent charge pump stage of said plurality of cascaded charge pump stages, and a second transfer transistor coupled between the second internal node and the intermediate node, the first and second transfer transistors being alternately operable, in respective half-periods of operation of said charge pump circuit,
• the first high voltage phase signal and the second high voltage phase signal have voltage dynamics higher than a maximum voltage sustainable by the first transfer transistor and the second transfer transistor,
• a protection stage coupled between the first and second internal nodes and the first and second transfer transistors so as to protect the first transfer transistor and the second transfer transistor from overvoltages present on the first internal node and second internal node.

A method of making a charge pump circuit comprising:

• coupling together in cascade, a plurality of charge pump stages cascaded to one another with each charge pump stage comprising
• a first pump capacitor coupled to a first internal node and configured to receive a first high voltage phase signal, and a second pump capacitor coupled to a second internal node and configured to receive a second high voltage phase signal, complementary with respect to the first high voltage phase signal,
• a first transfer transistor coupled between the first internal node and an intermediate node between said charge pump stage and a subsequent charge pump stage of said plurality of cascaded charge pump stages, and a second transfer transistor coupled between the second internal node and the intermediate node, the first and second transfer transistors being alternately operable, in respective half-periods of operation of said charge pump circuit,
• the first high voltage phase signal and the second high voltage phase signal have voltage dynamics higher than a maximum voltage sustainable by the first transfer transistor and the second transfer transistor,
• a protection stage coupled between the first and second internal nodes and the first and second transfer transistors so as to protect the first transfer transistor and the second transfer transistor from overvoltages present on the first internal node and second internal node.