Method of reading a ferroelectric memory cell
AssigneeTexas Instruments Incorporated
InventorSudhir K. Madan
Life of this patent
Estimating the term…
Abstract
A method of reading a memory cell. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low at t4, FIG. 10B) from the first bitline. A signal voltage (PL high at t4, FIG. 10B) from the memory cell is applied to a second bitline (BL) after the step of disconnecting. A difference voltage between the first and second bitlines is amplified (SAEN high at t7, FIGS. 8A and 10B).
Claims26
A method of reading a memory cell, comprising:
- precharging a first bitline to a base voltage;
- precharging a second bitline to the base voltage;
- connecting a reference voltage generator to the first bitline;
- charging the first bitline to a reference voltage from the reference voltage generator;
- disconnecting the reference voltage generator from the first bitline;
- applying a signal voltage from the memory cell to a second bitline after the step of disconnecting;
- and
- amplifying a difference voltage between the first and second bitlines.
A method of operating a memory system, comprising:
- precharging a plurality of first bitlines to a base voltage;
- precharging a plurality of second bitlines to the base voltage;
- connecting a reference voltage generator to the plurality of first bitlines;
- charging each of the first bitlines to a reference voltage from the reference voltage generator;
- disconnecting the reference voltage generator from the plurality of first bitlines;
- applying a respective signal voltage to each of the plurality of second bitlines from a respective memory cell after the step of disconnecting, wherein each of the second bitlines forms a bitline pair with one of the first bitlines;
- and
- amplifying a respective difference voltage between each bitline pair of the plurality of first and second bitlines.
A method of reading a memory cell, comprising:
- precharging the first bitline to a first voltage;
- floating the first bitline;
- precharging the second bitline to a second voltage different from the first voltage;
- floating the second bitline;
- applying a signal voltage from the memory cell to the second bitline after the step of floating the first and second bitlines;
- and
- amplifying a difference voltage between the first and second bitlines.
A memory array, comprising:
- a plurality of first bitlines comprising a first material;
- a plurality of second bitlines comprising the first material;
- at least one shield comprising the first material formed between at least one of the first bitlines and one of the second bitlines, said at least one shield being spaced apart from the at least one of the first bitlines and one of the second bitlines.
Dependencies are inferred from the claim text.