# US 8,570,809 B2 · Flash memory devices and systems

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- Number: US 8,570,809 B2
- Document ID: US8570809B2
- Status: Granted
- Kind: B2
- Application number: 13/340,091
- Filed: 2011-12-29
- Published: 2013-06-06
- Granted: 2013-10-29
- Earliest claimed: 2011-12-02
- Assignees: Cypress Semiconductor Corporation
- Applicants: Ryan T. Hirose; Bogdan Georgescu; Ashish Amonkar; Sean Mulholland; Vijay Raghavan; Cristinel Zonte
- Inventors: Ryan T. Hirose; Bogdan Georgescu; Ashish Amonkar; Sean Mulholland; Vijay Raghavan; Cristinel Zonte
- Web page: https://patentgrep.com/patent/US8570809B2

## CPC

- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/30: Power supply circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

## Claims

### Claim 1

A memory device, comprising:
an N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first source, a first gate, and a first drain coupled to a local bit line (BL);
a silicon-oxide-nitride-oxide silicon (SONOS) transistor comprising a second source, a second gate, and a second drain coupled to the first source of the nMOSFET; and
an isolated sector p-well (SPW) coupled to the nMOSFET and the SONOS transistor,
wherein the nMOSFET is a select transistor and is configured to isolate the SONOS transistor from the BL when the SONOS transistor is deselected during a read operation.

### Claim 2 (depends on 1)

The memory device of claim 1, further comprising:
a horizontal word line (WL) coupled to the first gate;
a horizontal SONOS word line (WLS) coupled to the second gate; and
a vertical local source line (SL) coupled to the second source.

### Claim 3 (depends on 2)

The memory device of claim 2, further comprising:
a first voltage input coupled to the WL;
a second voltage input coupled to the WLS;
a third voltage input coupled to the SL;
a fourth voltage input coupled to the isolated SPW; and
a current output coupled to the BL.

### Claim 4

A non-volatile (NV) memory, comprising:
an array of memory devices divided into a plurality of paired sectors;
a global bit line (GBL) coupled to each of the plurality of sectors, the GBL configured to provide high voltage to each respective sector during erase and program operations;
a plurality of local bit lines (BL) coupled to a plurality of memory devices in a column in the plurality of paired sectors, the BL configured to provide low voltage to the plurality of memory devices during read operations; and
a plurality of sense amplifiers, each sense amplifier coupled between a respective pair of sectors, the plurality of sense amplifiers coupled to a number of the plurality of BL in the paired sector,
wherein during a read operation the plurality of sense amplifiers reads the plurality of memory devices directly through the BL and not through the GBL.

### Claim 5 (depends on 4)

The NV memory of claim 4, wherein each memory device comprises:
an N-channel metal oxide semiconductor field-effect transistor (nMOSFET);
a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET; and
an isolated p-well (SPW) coupled to the nMOSFET and the SONOS transistor.

### Claim 6 (depends on 5)

The NV memory of claim 5, wherein:
the nMOSFET comprises a first source, a first gate, and a first drain; and
the SONOS transistor comprises a second source, a second gate, and a second drain coupled to the first source.

### Claim 7 (depends on 6)

The NV memory of claim 6, wherein each memory device further comprises:
a first word line (WL) coupled to the first gate;
a second word line (WLS) coupled to the second gate;
a local source line (SL) coupled to the second source; and
wherein the first drain is coupled to the BL, and wherein the BL is configured to provide low voltage to the first drain during read operations.

### Claim 8 (depends on 7)

The NV memory of claim 7, wherein each memory device further comprises:
a first voltage input coupled to the WL;
a second voltage input coupled to the WLS;
a third voltage input coupled to the SL;
a fourth voltage input coupled to the isolated (SPW); and
a current output coupled to the BL.

### Claim 9 (depends on 6)

The NV memory of claim 6, wherein each sense amplifier comprises:
a first multiplexer (MUX) coupled to the second source of each memory device in a first sector;
a second MUX coupled to the second source of each memory device in a second sector; and
a sense amplifier comprising a first input coupled to the first MUX, a second input coupled to the second MUX, and an output coupled to the voltage output.

### Claim 10 (depends on 6)

The NV memory of claim 6, wherein the nMOSFET is a select transistor and is configured to isolate the SONOS transistor from the BL when the SONOS transistor is deselected during a read operation.

### Claim 11 (depends on 4)

The NV memory of claim 4, comprising a number of paired sectors in the range of four paired sectors and sixty-four paired sectors.

### Claim 12 (depends on 11)

The NV memory of claim 11, wherein at least one pair of the paired sectors is a supervisor memory sector for the flash memory.

### Claim 13 (depends on 4)

The NV memory of claim 4, wherein each sector comprises:
a plurality of rows of the memory devices; and
a plurality of columns of the memory devices.

### Claim 14 (depends on 13)

The NV memory of claim 13, wherein:
the plurality of rows of the memory devices comprises a number of rows of the memory devices in the range of 2 rows of the memory devices and 1024 rows of the memory devices; and
the plurality of columns of the memory devices comprises a number of columns of the memory devices in the range of eight columns of the memory devices and 16384 columns of the memory devices.

### Claim 15 (depends on 14)

The NV memory of claim 14, wherein each sector comprises 256 rows of the memory devices and 4096 columns of the memory devices.

### Claim 16

A method for operating a flash memory system comprising an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) coupled to each of the plurality of sectors, and a local bit line (BL) coupled to each memory device, the method comprising:
providing high voltage to the BL in any or all sectors during erase and program operations, the high voltage provided by the GBL; and
providing low voltage from a sense amplifier to a number of memory devices in of any or all sectors during read operations directly through the BL and not through the GBL.

### Claim 17 (depends on 16)

The method of claim 16, further comprising preventing high voltage from being provided by the GBL to each sector during read operations.

### Claim 18 (depends on 16)

The method of claim 16, wherein providing the high voltage comprises providing a first voltage to a selected sector via the GBL and providing a second voltage to a de-selected sector via the GBL, wherein:
the first voltage is greater than the second voltage during erase operations; and
the second voltage is greater than the first voltage during program operations.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the first high voltage is about 4.3 volts and the second high voltage is about 1.2 volts during erase operations; and
the first high voltage is about −3.2 volts and the second high voltage is about 0 volts during program operations.

### Claim 20 (depends on 16)

The method of claim 16, wherein the sense amplifier is a differential sense amplifier comprising first and second inputs, and wherein during read operations the BL in one sector comprising the memory device being read is connected to the first input of the local differential SA, while the BL in the other sector of the paired sectors is connected to the second input to form matched current inputs to the differential sense amplifier.