# US 8,570,808 B2 · Nonvolatile memory device with 3D memory cell array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,808 B2 - Document ID: US8570808B2 - Status: Granted - Kind: B2 - Application number: 13/186,987 - Filed: 2011-07-20 - Published: 2012-02-09 - Granted: 2013-10-29 - Earliest claimed: 2010-08-09 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Jung-hoon Park; Kyung-Hwa Kang; Chi-Weon Yoon; Sang-Wan Nam; Sung-Won Yun - Inventors: Jung-hoon Park; Kyung-Hwa Kang; Chi-Weon Yoon; Sang-Wan Nam; Sung-Won Yun - Web page: https://patentgrep.com/patent/US8570808B2 ## CPC - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time. ## Claims ### Claim 1 A nonvolatile memory device comprising: a three-dimensional memory cell array including a plurality of memory cells arranged in a plurality memory cell array layers stacked on a substrate, such that a plurality of words lines extends across the plurality of memory cell array layers from a lowest memory cell array layer closest to the substrate to a highest memory cell array layer farthest from the substrate; a voltage generator circuit that generates a first voltage signal and a second voltage signal; and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line among the plurality of word lines and the second voltage signal to an unselected word line among the plurality of word lines, wherein the selected word line and the unselected word line have different resistances, the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time, and during the defined period of time the voltage generator circuit increases the first voltage signal and the second voltage signal from a first level to a second level. ### Claim 2 (depends on 1) The nonvolatile memory device of claim 1, wherein the first level is ground and the second level is a pass voltage level. ### Claim 3 (depends on 1) The nonvolatile memory device of claim 1, wherein the first level is a pass voltage level and the second level is a program voltage level. ### Claim 4 (depends on 1) The nonvolatile memory device of claim 1, wherein the voltage generator circuit comprises: a first voltage generator that stepwise generates the first voltage signal to a program voltage level; and a second voltage generator that stepwise generates the second voltage signal stepwise to a pass voltage level. ### Claim 5 (depends on 1) The nonvolatile memory device of claim 1, further comprising control logic that controls operation of the voltage generator circuit and the row selecting circuit. ### Claim 6 (depends on 5) The nonvolatile memory device of claim 5, wherein the control logic comprises ramping logic that defines the rising slope. ### Claim 7 (depends on 5) The nonvolatile memory device of claim 5, further comprising a ramping control unit separate from the control logic that controls the voltage generator circuit to define the rising slope. ### Claim 8 (depends on 5) The nonvolatile memory device of claim 5, wherein the row selecting circuit comprises: a word line driver that receives the first and second voltage signals; a ramper configured to adjust respective first and second rising slopes for the first and second voltage signals to generate first and second driving signals; and a row decoder that selectively applies the first and second driving signals to the plurality of word lines. ### Claim 9 (depends on 8) The nonvolatile memory device of claim 8, wherein the ramper is configured within the word line driver. ### Claim 10 (depends on 8) The nonvolatile memory device of claim 8, wherein the ramper is configured within the word line driver. ### Claim 11 (depends on 1) The nonvolatile memory device of claim 1, wherein the first level is ground and the second level is a non-selection read voltage level. ### Claim 12 (depends on 1) The nonvolatile memory device of claim 1, wherein the first level is a non-selection read level and the second level is a selection read level. ### Claim 13 A nonvolatile memory device comprising: a three-dimensional (3D) memory cell array including a plurality of memory cells arranged in a plurality memory cell array layers stacked on a substrate, such that a plurality of words lines extends across the plurality of memory cell array layers from a lowest memory cell array layer closest to the substrate to a highest memory cell array layer farthest from the substrate, wherein the 3D memory cell array comprises a pillar that extends through the plurality of memory cell array layers and that progressively narrows in width as it extends from the highest memory cell array layer to the lowest memory cell array layer; a voltage generator circuit that generates a first voltage signal and a second voltage signal; and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line among the plurality of word lines and the second voltage signal to an unselected word line among the plurality of word lines, wherein each one of the plurality of words lines intersects the pillar with a different cross-sectional area, such that the selected word line and the unselected word line have different resistances, and the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time. ### Claim 14 (depends on 13) The nonvolatile memory device of claim 13, wherein during the defined period of time the voltage generator circuit increases the first voltage signal and the second voltage signal from a first level to a second level. ### Claim 15 (depends on 14) The nonvolatile memory device of claim 14, wherein the first level is ground and the second level is a pass voltage level. ### Claim 16 (depends on 15) The nonvolatile memory device of claim 15, wherein the first level is a pass voltage level and the second level is a program voltage level. ### Claim 17 (depends on 13) The nonvolatile memory device of claim 13, wherein the voltage generator circuit comprises: a first voltage generator that stepwise generates the first voltage signal to a program voltage level; and a second voltage generator that stepwise generates the second voltage signal stepwise to a pass voltage level. ### Claim 18 (depends on 13) The nonvolatile memory device of claim 13, further comprising control logic that controls operation of the voltage generator circuit and the row selecting circuit. ### Claim 19 (depends on 18) The nonvolatile memory device of claim 18, wherein the row selecting circuit comprises: a word line driver that receives the first and second voltage signals; a ramper configured to adjust respective first and second rising slopes for the first and second voltage signals to generate first and second driving signals; and a row decoder that selectively applies the first and second driving signals to the plurality of word lines.