# US 8,570,805 B2 · Nonvolatile memory device, programming method thereof and memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,805 B2 - Document ID: US8570805B2 - Status: Granted - Kind: B2 - Application number: 13/029,518 - Filed: 2011-02-17 - Published: 2011-08-18 - Granted: 2013-10-29 - Earliest claimed: 2010-02-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Changhyun Lee; Jinman Han; Doogon Kim; Sunghoi Hur; Jongin Yun - Inventors: Changhyun Lee; Jinman Han; Doogon Kim; Sunghoi Hur; Jongin Yun - Web page: https://patentgrep.com/patent/US8570805B2 ## CPC - G11C 16/107: {Programming all cells in an array, sector or block to the same state prior to flash erasing} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - G11C 2213/71: Three dimensional array - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. ## Claims ### Claim 1 A programming method of a nonvolatile memory device including a substrate, and a plurality of memory strings each memory string including a plurality of memory cells stacked in the direction vertical to the substrate, the programming method comprising: applying a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cells to be programmed; applying a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cells to be program-prohibited; applying a third voltage to selected string selection lines connected to at least two memory strings in same row; applying a fourth voltage to unselected string selection lines connected to at least two memory strings in same row; and applying a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string; wherein the first to third voltages are positive voltages, wherein each memory string includes at least two string selection transistors connected in series between memory cells of each memory string and bit lines. ### Claim 2 (depends on 1) The programming method of claim 1, wherein: the first voltage has a lower level than the second voltage, the fourth voltage has a lower level than the third voltage, and the fourth voltage has a lower level than the first voltage. ### Claim 3 (depends on 1) The programming method of claim 1, wherein the applying the program operation voltage comprises applying a pass voltage to the plurality of word lines and then applying to a program voltage to a selected word line. ### Claim 4 (depends on 1) The programming method of claim 1, wherein: partial lines of the plurality of word lines, which are connected to memory cells disposed at the same height from the substrate, are connected in common, and the program operation voltage is applied to the partial lines which are connected in common. ### Claim 5 (depends on 1) The programming method of claim 1, wherein the fourth voltage is a positive voltage. ### Claim 6 (depends on 5) The programming method of claim 5, wherein the fourth voltage has a lower level than the third voltage. ### Claim 7 (depends on 5) The programming method of claim 5, wherein the first voltage has a lower level than the second voltage. ### Claim 8 (depends on 5) The programming method of claim 5, wherein the first voltage has the same level as a level of the fourth voltage. ### Claim 9 (depends on 5) The programming method of claim 5, further comprising applying a ground voltage to the unselected string selection lines before the applying the program operation voltage to the plurality of word lines. ### Claim 10 (depends on 9) The programming method of claim 9, wherein the fourth voltage has the same level as a level of the third voltage. ### Claim 11 (depends on 9) The programming method of claim 9, further comprising applying a fifth voltage having a lower level than the first voltage to the selected bit line before the applying a program operation voltage to a plurality of word lines. ### Claim 12 (depends on 11) The programming method of claim 11, wherein the fifth voltage has a positive level. ### Claim 13 (depends on 11) The programming method of claim 11, wherein the first positive voltage has the same level as a level of the second positive voltage. ### Claim 14 (depends on 1) The programming method of claim 1, wherein a channel voltage of the selected memory cell is formed as a positive voltage while the program operation voltage is being applied. ### Claim 15 A nonvolatile memory device comprising: a memory cell array comprising a substrate and a plurality of memory cells which are stacked in a direction vertical to the substrate; and a reading and writing circuit connected to the memory cell array through a plurality of bit lines, wherein in a programming operation, the reading and writing circuit applies a first positive voltage to at least one bit line corresponding to memory cells to be programmed and a second positive voltage to at least one bit line corresponding to memory cells to be program-prohibited, wherein groups of the plurality of memory cells respectively configure NAND strings, and the bit lines are respectively connected to at least two of the NAND strings, wherein each NAND string includes at least two selection transistors connected in series between memory cells of each NAND string and the bit lines. ### Claim 16 (depends on 15) The nonvolatile memory device of claim 15, wherein the first positive voltage has a lower level than the second positive voltage. ### Claim 17 (depends on 15) The nonvolatile memory device of claim 15, wherein the nonvolatile memory device further comprises a decoder transferring a program operation voltage to word lines connected to the at least two NAND strings, in the programming operation. ### Claim 18 (depends on 17) The nonvolatile memory device of claim 17, wherein the program operation voltage comprises a program voltage transferred to a selected word line, and a pass voltage transferred to unselected word lines. ### Claim 19 (depends on 17) The nonvolatile memory device of claim 17, wherein each of the NAND strings is extended in a direction vertical to the substrate and is connected to a corresponding bit line among the bit lines. ### Claim 20 (depends on 15) The nonvolatile memory device of claim 15, wherein the reading and writing circuit comprises a plurality of page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises: a latch receiving and storing a writing data in a programming operation; a bias circuit setting up a corresponding bit line to the first positive voltage when the writing data stored in the latch is a program data. ### Claim 21 (depends on 15) The nonvolatile memory device of claim 15, further comprising a decoder connected to the memory cell array through word lines and selection lines connected to the selection transistors of the NAND strings respectively, wherein: in the programming operation, the reading and writing circuit applies a first positive voltage to a selected bit line and applies a second positive voltage to an unselected bit line, in the programming operation, the decoder applies a third positive voltage to selected selection lines among the selection lines, applies a fourth positive voltage to unselected selection lines, and applies a program operation voltage to the word lines. ### Claim 22 (depends on 21) The nonvolatile memory device of claim 21, wherein in the programming operation, the decoder further applies the fourth positive voltage larger than a ground voltage to the unselected selection lines and then applies a ground voltage to the unselected selection lines. ### Claim 23 A memory system comprising: a nonvolatile memory device; and a controller controlling the nonvolatile memory device, wherein the nonvolatile memory device comprises: a memory cell array comprising a substrate and a plurality of memory cells which are stacked in a direction vertical to the substrate; and a reading and writing circuit connected to the memory cell array through bit lines, wherein in a programming operation, the reading and writing circuit applies a positive voltage to bit lines corresponding to memory cells to be programmed, wherein groups of the plurality of memory cells respectively configure NAND strings, and the bit lines are respectively connected to at least two of the NAND strings respectively, wherein each NAND string includes at least two selection transistors connected in series between memory cells of each NAND string and the bit lines. ### Claim 24 (depends on 23) The memory system of claim 23, wherein the controller and the nonvolatile memory device configure a semiconductor drive (Solid State Drive (SSD)). ### Claim 25 (depends on 23) The memory system of claim 23, wherein the controller and the nonvolatile memory device configure a memory card.