# US 8,570,802 B2 · Nonvolatile semiconductor memory device capable of speeding up write operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,802 B2 - Document ID: US8570802B2 - Status: Granted - Kind: B2 - Application number: 13/235,396 - Filed: 2011-09-18 - Published: 2012-11-15 - Granted: 2013-10-29 - Earliest claimed: 2011-05-12 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Masanobu Shirakawa - Inventors: Masanobu Shirakawa - Web page: https://patentgrep.com/patent/US8570802B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects a first string selected as a sample from the memory cell array, and writes data to the memory cell. The memory unit holds, for each word line, the number of write operations to each memory cell of the first string. When data is written to each memory cell of a second string other than the first string, the voltage generation unit generates an initial write voltage based on the number of write operations, which corresponds to the selected word line and is read out from the memory unit. ## Claims ### Claim 1 A nonvolatile semiconductor memory device comprising: a memory cell array including a first string and a second string, the first string including a plurality of first memory cells, the second string including a plurality of second memory cells, the plurality of first memory cells being connected to first word lines respectively, the plurality of second memory cells being connected to second word lines respectively, the plurality of first memory cells and the plurality of second memory cells being stacked above a semiconductor substrate; and a controller configured to control a first program operation and a second program operation, the controller configured to supply a first voltage to a selected first word line at a beginning of the first program operation, the controller configured to supply a second voltage to the selected first word line after supplying the first voltage, the second voltage being generated by adding a step-up voltage to the first voltage in the first program operation, the controller configured to supply a third voltage to a selected second word line at the beginning of the second program operation after the first program operation, a difference between the first voltage and the third voltage being substantially k (k is natural number) times width of the step-up voltage. ### Claim 2 (depends on 1) The device according to claim 1, wherein if a threshold voltage of the memory cell has not reached a verify voltage, the controller steps up a program voltage, and executes the first and second program operations, the program voltage including the first voltage, the second voltage, and the third voltage. ### Claim 3 (depends on 1) The device according to claim 1, wherein if the number of memory cells having threshold voltages that exceed a verify voltage is smaller than a first value, the controller steps up a program voltage, and executes the first and second program operations. ### Claim 4 (depends on 3) The device according to claim 3, wherein the first and second strings are formed by stacking the plurality of first and second memory cells above the semiconductor substrate. ### Claim 5 (depends on 3) The device according to claim 3, wherein the first and second strings comprise: a first portion in which the plurality of first memory cells and a first select gate are stacked above a semiconductor substrate while sharing a first pillar portion, the plurality of first memory cells are connected to first word lines, and the first select gate is connected to a first select gate line; a second portion in which the plurality of second memory cells and a second select gate are stacked above the semiconductor substrate while sharing a second pillar portion, the plurality of second memory cells are connected to second word lines, and the second select gate is connected to a second select gate line; a third portion which is provided in the semiconductor substrate and configured to electrically connect the first pillar portion and the second pillar portion; a bit line connected to the first portion via the first select gate; and a source line connected to the second portion via the second select gate. ### Claim 6 (depends on 5) The device according to claim 5, wherein the selected first word line is a same layer as the selected second word line. ### Claim 7 (depends on 5) The device according to claim 5, wherein the first string comprises the plurality of first memory cells and a first select gate stacked above a semiconductor substrate while sharing a first pillar portion, and the second string comprises the plurality of second memory cells and a second select gate stacked above the semiconductor substrate while sharing a second pillar portion. ### Claim 8 (depends on 7) The device according to claim 7, wherein the selected first word line is a same layer as the selected second word line. ### Claim 9 (depends on 3) The device according to claim 3, wherein each of the plurality of memory cells stores data of not less than 2 bits, and the memory unit stores the first number of first program operations for each of the first word lines and the second number of the second program operations for each of the second word lines. ### Claim 10 (depends on 9) The device according to claim 9, wherein in writing data of a first bit, the controller generates an initial program voltage used to program the data of the first bit, based on the first and second numbers. ### Claim 11 (depends on 1) The device according to claim 1, further comprising: a voltage generation unit, the controller configured to control the voltage generation unit. ### Claim 12 (depends on 11) The device according to claim 11, wherein the controller comprises: a first storing unit configured to store the number of write pulses for the first string; a storing unit configured to store an initial program voltage; and an arithmetic unit configured to calculate an optimum program voltage based on the number of program pulses from the first storing unit and the initial program voltage from the storing unit. ### Claim 13 (depends on 11) The device according to claim 11, wherein the arithmetic unit calculates the initial program voltage WLn Initial VPGM of the selected word line based on WLn Initial VPGM=(Initial VPGM)+{(WLn loop#)−Wm+1}×ΔVPGM where the Initial VPGM is the initial program voltage, the WLn loop# is the number of program operations, the Wm is the number of program operations of the second string, and the ΔVPGM is an increment of the program voltage. ### Claim 14 (depends on 1) The nonvolatile semiconductor memory device according to claim 1, the memory cell array including a plurality of blocks, each block including a plurality of strings, the plurality of strings including the first string and the second string, the plurality of strings being connected a plurality of bit lines, one of the bit lines being connected to a plurality of strings in each block. ### Claim 15 (depends on 1) The device according to claim 1, wherein the number of first word lines is L (L is natural number), the number of second word lines is L, and the controller is configured to select M-th (M is natural number, M is equal to or less L) second word line as the selected second word line when the controller is configured to select M-th first word line as the selected first word line. ### Claim 16 A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of blocks, each block including a plurality of strings, the plurality of strings including a first string and a second string, the first string including a plurality of first memory cells, the second string including a plurality of second memory cells, the plurality of first memory cells being connected to first word lines respectively, the plurality of second memory cells being connected to second word lines respectively, the plurality of first memory cells and the plurality of second memory cells being stacked above a semiconductor substrate; and a controller configured to control a first program operation and a second program operation, the controller configured to supply a first voltage to a selected first word line at a beginning of the first program operation, the controller configured to supply a second voltage to the selected first word line after supplying the first voltage, the second voltage being generated by adding a step-up voltage to the first voltage in the first program operation, the controller configured to supply a third voltage to a selected second word line at the beginning of the second program operation after the first program operation, a difference between the first voltage and the third voltage being substantially k (k is a natural number) times width of the step-up voltage. ### Claim 17 (depends on 16) The device according to claim 16, wherein if a threshold voltage of the memory cell has not reached a verify voltage, the controller steps up a program voltage, and executes the first and second program operations, the program voltage including the first voltage, the second voltage, and the third voltage. ### Claim 18 (depends on 16) The device according to claim 16, wherein if the number of memory cells having threshold voltages that exceed a verify voltage is smaller than a first value, the controller steps up a program voltage, and executes the first and second program operations. ### Claim 19 (depends on 18) The device according to claim 18, wherein the first and second strings are formed by stacking the plurality of first and second memory cells above the semiconductor substrate. ### Claim 20 (depends on 18) The device according to claim 18, wherein the first and second strings comprise: a first portion in which the plurality of first memory cells and a first select gate are stacked above a semiconductor substrate while sharing a first pillar portion, the plurality of first memory cells are connected to first word lines, and the first select gate is connected to a first select gate line; a second portion in which the plurality of second memory cells and a second select gate are stacked above the semiconductor substrate while sharing a second pillar portion, the plurality of second memory cells are connected to second word lines, and the second select gate is connected to a second select gate line; a third portion which is provided in the semiconductor substrate and configured to electrically connect the first pillar portion and the second pillar portion; a bit line connected to the first portion via the first select gate; and a source line connected to the second portion via the second select gate. ### Claim 21 A method of controlling a nonvolatile semiconductor memory system, the nonvolatile semiconductor memory system including a memory cell array, the memory cell array including a first string and a second string, the first string including a plurality of first memory cells, the second string including a plurality of second memory cells, the plurality of first memory cells being connected to first word lines respectively, the plurality of second memory cells being connected to second word lines respectively, the plurality of first memory cells and the plurality of second memory cells being stacked above a semiconductor substrate, the method comprising: executing a first program operation; and executing a second program operation; applying a first voltage to a selected first word line at the beginning of the first program operation, and applying a second voltage to the selected first word line after applying the first voltage in the first program operation, the second voltage being generated by adding a step-up voltage to the first voltage, and applying a third voltage to a selected second word line at the beginning of the second program operation after the first program operation, a difference between the first voltage and the third voltage being substantially k (k is natural number) times width of the step-up voltage. ### Claim 22 (depends on 21) The method according to claim 21, wherein if a threshold voltage of the memory cell has not reached a verify voltage, a program voltage is stepped up, and the first and second program operations are executed, wherein the program voltage includes the first voltage, the second voltage, and the third voltage. ### Claim 23 (depends on 21) The method according to claim 21, wherein if the number of memory cells having threshold voltages that exceed a verify voltage is smaller than a first value, a program voltage is stepped up, and the first and second program operations are executed, wherein the program voltage includes the first voltage, the second voltage, and the third voltage. ### Claim 24 (depends on 23) The method according to claim 23, wherein the first and second strings are formed by stacking a plurality of memory cells above the semiconductor substrate. ### Claim 25 (depends on 23) The method according to claim 23, wherein the first and second strings comprise: a first portion in which the plurality of first memory cells and a first select gate are stacked above a semiconductor substrate while sharing a first pillar portion, the plurality of first memory cells are connected to first word lines, and the first select gate is connected to a first select gate line; a second portion in which the plurality of second memory cells and a second select gate are stacked above the semiconductor substrate while sharing a second pillar portion, the plurality of second memory cells are connected to second word lines, and the second select gate is connected to a second select gate line; a third portion which is provided in the semiconductor substrate and configured to electrically connect the first pillar portion and the second pillar portion; a bit line connected to the first portion via the first select gate; and a source line connected to the second portion via the second select gate. ### Claim 26 (depends on 23) The method according to claim 23, wherein each of the plurality of memory cells stores data of not less than 2 bits, and the memory unit stores the first number of first program operations for each of the first word lines and the second number of the second program operations for each of the second word lines. ### Claim 27 (depends on 26) The method according to claim 26, wherein in writing data of a first bit, an initial program voltage used to program the data of the first bit is generated based on the first and second numbers.