# US 8,570,801 B2 · Method of programming a semiconductor memory device

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- Number: US 8,570,801 B2
- Document ID: US8570801B2
- Status: Granted
- Kind: B2
- Application number: 12/982,324
- Filed: 2010-12-30
- Published: 2011-12-08
- Granted: 2013-10-29
- Earliest claimed: 2010-06-04
- Assignees: Hynix Semiconductor Inc.
- Applicants: Sang Oh Lim; Jin Su Park
- Inventors: Sang Oh Lim; Jin Su Park
- Web page: https://patentgrep.com/patent/US8570801B2

## CPC

- G11C 16/10: Programming or data input circuits
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method of programming a semiconductor memory device includes the steps of grouping memory cells in accordance with levels of threshold voltages to be programmed, programming the memory cell groups by sequentially applying program voltages to the memory cell groups, and program-verifying the memory cell groups.

## Claims

### Claim 1

A method of programming a semiconductor memory device, the method comprising:
grouping memory cells into memory cell groups in accordance with target program voltage levels;
performing program operations on the memory cell groups by sequentially applying program voltages corresponding to the target program voltage levels to the memory cell groups; and
program-verifying the memory cell groups in sequence after the program operations on all of the memory cell groups are performed.

### Claim 2 (depends on 1)

The method of claim 1, wherein the program operations start with a program voltage corresponding to the lowest threshold voltage and ends with a program voltage corresponding to the highest threshold voltage.

### Claim 3 (depends on 1)

The method of claim 1, wherein, while applying the program voltage to one of the memory cell groups, the others of the memory cell groups are inhibited from being programmed.

### Claim 4

A method of programming a semiconductor memory device, memory cells of which are programmed to have one of first to third threshold voltage distributions, the method comprising:
applying a first program voltage to program a first memory cell group whose threshold voltages are to be shifted into the first threshold voltage distribution;
applying a second program voltage to program a second memory cell group whose threshold voltages are to be shifted into the third threshold voltage distribution; and
program-verifying the first and second memory cell groups in sequence after the first program voltage is applied to the first memory cell group and the second program voltage is applied to the second memory cell group.

### Claim 5 (depends on 4)

The method of claim 4, further comprising, before the application of the first program voltage, setting a bit line voltage to inhibit the second memory cell group from being programmed.

### Claim 6 (depends on 4)

The method of claim 4, further comprising, before the application of the second program voltage, setting a bit line voltage to inhibit the first memory cell group from being programmed.

### Claim 7 (depends on 4)

The method of claim 4, wherein the first memory cell group includes memory cells whose threshold voltages are to be shifted into the second threshold voltage distribution.

### Claim 8 (depends on 4)

The method of claim 4, wherein the second memory cell group includes memory cells whose threshold voltages are to be shifted into the second threshold voltage distribution.

### Claim 9

A method of programming a semiconductor memory device, memory cells of which are programmed to have one of first to third threshold voltage distributions, the method comprising:
applying a first program voltage to program a first memory cell group whose threshold voltages are to be shifted into the first threshold voltage distribution;
applying a second program voltage to program a second memory cell group whose threshold voltages are to be shifted into the second third threshold voltage distribution;
applying a third program voltage to program a third memory cell group whose threshold voltages are to be shifted into the third threshold voltage distribution; and
program-verifying the first through third memory cell groups in sequence after the first program voltage is applied to the first memory cell group, the second program voltage is applied to the second memory cell group, and the third program voltage is applied to the third memory cell group.

### Claim 10 (depends on 9)

The method of claim 9, further comprising, before the application of the first program voltage, setting a bit line voltage to inhibit the second and third memory cell groups from being programmed.

### Claim 11 (depends on 9)

The method of claim 9, further comprising, before the application of the second program voltage, setting a bit line voltage to inhibit the first and third memory cell groups from being programmed.

### Claim 12 (depends on 9)

The method of claim 9, further comprising, before the application of the third program voltage, setting a bit line voltage to inhibit the first and second memory cell groups from being programmed.