# US 8,570,800 B2 · Memory using a plurality of diodes as program selectors with at least one being a polysilicon diode

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- Number: US 8,570,800 B2
- Document ID: US8570800B2
- Status: Granted
- Kind: B2
- Application number: 13/026,692
- Filed: 2011-02-14
- Published: 2012-02-23
- Granted: 2013-10-29
- Earliest claimed: 2010-08-20
- Applicants: Shine C. Chung
- Inventors: Shine C. Chung
- Web page: https://patentgrep.com/patent/US8570800B2

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 11/1659: {Cell access}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 17/16: using electrically-fusible links
- G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)}
- H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/74: Array wherein each memory cell has more than one access device
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes with P+ and N+ implants in two ends. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The memory cells can be used to construct a two-dimensional memory array with the N-terminals of the first diodes and the P-terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline.

## Claims

### Claim 1

A memory, comprising:
a plurality of memory cells, each of the memory cells including a memory element with first and second terminals, and first and second diodes as program selectors, the first and second diodes having a first terminal associated with a first type of dopant and a second terminal associated with a second type of dopant, the first diode having the first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element;
a plurality of local wordlines, each coupled to a plurality of the memory cells via the second terminal of the first diodes or to the first terminal of the second diode and having a first resistivity;
a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and
a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element,
wherein, for each of the memory cells, the memory element is configured to be programmable by turning on the first diode while cutting off the second diode for one state and by turning on the second diode while cutting off the first diode for another state.

### Claim 2 (depends on 1)

A memory as recited in claim 1, wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagentic as a fixed-layer stack, another multi-layer of ferromagnetic or anti-ferromagentic stack as a free-layer stack, and a dielectric layer in between the stacks.

### Claim 3 (depends on 1)

A memory as recited in claim 1, wherein the memory element comprises a metal-oxide film between metal or metal alloy electrodes.

### Claim 4 (depends on 1)

A memory as recited in claim 1, wherein the memory element comprises a solid-state electrolyte film between metal or metal alloy electrodes.

### Claim 5 (depends on 1)

A memory as recited in claim 1, wherein one or both of the first and second diodes are built on a polysilicon structure.

### Claim 6 (depends on 1)

A memory as recited in claim 1, wherein, for each of the memory cells, the second terminal of the first diode is coupled to the first terminal of the second diode.

### Claim 7 (depends on 1)

A memory as recited in claim 1, wherein the local wordline is at least in part constructed from a polysilicon.

### Claim 8 (depends on 1)

A memory as recited in claim 1, wherein the global wordline is constructed of metal.

### Claim 9 (depends on 1)

A memory as recited in claim 1, wherein the global wordline is coupled to the local wordline through at least one of conductive via or contact.

### Claim 10 (depends on 1)

A memory as recited in claim 1, wherein the bitline is coupled to a first supply voltage line and the global wordline is coupled to a second supply voltage line during program or read, and wherein the voltage between the first and second supply voltages has a larger magnitude or longer duration for program than read.

### Claim 11 (depends on 1)

A memory as recited in claim 1, wherein the bitline is coupled to a first supply voltage line and the global wordline is coupled to a second supply voltage line during program, and wherein the voltage between the first and second supply voltages lines has one polarity for one state and another polarity for another state.

### Claim 12 (depends on 1)

A memory as recited in claim 1, wherein the memory further comprising a plurality of write bitline selectors to select a bitline coupled to a first supply voltage line, and a plurality of wordline drivers to select a local wordline coupled to a second supply voltage line to conduct a current during program.

### Claim 13 (depends on 1)

A memory as recited in claim 1, wherein the memory further comprising a plurality of read bitline selectors to select a bitline coupled to a sense amplifier, and a plurality of wordline drivers to select a local wordline coupled to a supply voltage to conduct a current through the sense amplifier during read.

### Claim 14

An electronic system, comprising:
a processor; and
a memory operatively connected to the processor, the memory including at least:
a plurality of memory cells, each of the memory cells including a memory element with first and second terminals, and first and second diodes as program selectors, the first and second diodes having a first terminal from a first active region with a first type of dopant and a second terminal from a second active region with a second type of dopant, the first diode having the first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element;
a plurality of local wordlines, each coupled to a plurality of the memory cells via the second terminal of the first diodes or to the first terminal of the second diode and having a first resistivity;
a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and
a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element,
wherein, for each of the memory cells, the memory element is configured to be programmable by turning on the first diode while cutting off the second diode for one state and by turning on the second diode while cutting off the first diode for another state.

### Claim 15 (depends on 14)

An electronic system as recited in claim 14, wherein at least one of the first and second diodes is built on a polysilicon structure.

### Claim 16 (depends on 14)

An electronic system as recited in claim 14, wherein, in each of the memory cells, the second terminal of the first diode is coupled to the first terminal of the second diode.

### Claim 17 (depends on 14)

An electronic system as recited in claim 14, wherein the electronic system is configured to periodically read content of the memory cells and write it back. The period is longer than a second.

### Claim 18 (depends on 14)

An electronics system as recited in claim 14, wherein the memory is configured to periodically read content of the memory cells and writes it back. The mechanism is controlled external to the memory.

### Claim 19

A method for programming a memory comprises:
providing a plurality of memory cells, each memory cell including a memory element with first and second terminals, and first and second diodes as program selectors; the diodes having a first terminal associated with a first type of dopant and a second terminal associated with a second type of dopant; the first diode having the first terminal coupled to the second terminal of the memory element, the second diode having the second terminal coupled to the second terminal of the memory element;
providing a plurality of local wordlines, each coupled to a plurality of the memory cells in the second terminal of the first diodes or to the first terminal of the second diodes and having a first resistivity;
providing a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity;
providing a plurality of bitlines, each coupled to a plurality of the memory cells in the first terminal of memory element; and
programming at least one selected memory cell selected from the plurality of memory cells by applying a first supply voltage to at least one selected bitlines and a second supply voltage to at least one selected global wordlines.

### Claim 20 (depends on 19)

A method as recited in claim 19, wherein to program the at least one selected memory cell to one state by conducting the first diode in one current direction, and to program the at least one selected memory cell to another state by conducting the second diode in another current direction.

### Claim 21 (depends on 19)

A method as recited in claim 19,
wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagentic as a fixed-layer stack, another multi-layer of ferromagnetic or anti-ferromagentic stack as a free-layer stack, and a dielectric layer in between the stacks,
wherein at least one of the first and second diodes is built on a polysilicon structure, and
wherein, for each of the memory cells, the second terminal of the first diode is coupled to the first terminal of the second diode.