# US 8,570,799 B2 · Magnetic random access memory with conversion circuitry

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,570,799 B2
- Document ID: US8570799B2
- Status: Granted
- Kind: B2
- Application number: 13/210,460
- Filed: 2011-08-16
- Published: 2013-02-21
- Granted: 2013-10-29
- Earliest claimed: 2011-08-16
- Assignees: Intel Mobile Communications GmbH
- Applicants: Uwe Hildebrand; Josef Hausner; Matthias Obermeier; Daniel Bergmann
- Inventors: Uwe Hildebrand; Josef Hausner; Matthias Obermeier; Daniel Bergmann
- Web page: https://patentgrep.com/patent/US8570799B2

## CPC

- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

## Claims

### Claim 1

A magnetic random access memory device, comprising:
a magnet random access memory configured as a read/write memory, and
a conversion circuitry configured to convert at least a first section of the magnet random access memory to a read only memory,
wherein the conversion circuitry is configured to convert the at least first section to the read only memory in an irreversible manner, and
wherein the device further comprises at least one write line, and the conversion circuitry comprises a fuse electrically connected to the write line.

### Claim 2

A magnetic random access memory device, comprising:
a magnet random access memory configured as a read/write memory, and
a conversion circuitry configured to convert at least a first section of the magnet random access memory to a read only memory,
wherein the conversion circuitry is configured to convert the at least first section to the read only memory back to the read/write memory in a reversible manner, and
wherein the conversion circuitry comprises a storage medium configured to store an information indicating whether a section of the first memory section can be written upon or not.

### Claim 3 (depends on 2)

The magnetic random access memory device according to claim 2, wherein the storage medium comprises a plurality of bit positions, wherein each one of the bit positions is associated with one section of the magnetic random access memory.

### Claim 4

A data processing system, comprising:
a semiconductor chip,
a processing unit,
a magnetic random access memory,
a static random access memory, and
a bus system connecting the processing unit, the static random access memory, and the magnetic random access memory with each other,
wherein the magnetic random access memory and the static random access memory are integrated on the semiconductor die.

### Claim 5 (depends on 4)

The data processing system according to claim 4, wherein the magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

### Claim 6 (depends on 4)

The data processing system according to claim 4, further comprising:
a conversion circuitry configured to convert at least a first section of the magnetic random access memory to a read only memory.

### Claim 7 (depends on 4)

The data processing system according to claim 4, wherein the processing unit is a digital signal processor.

### Claim 8 (depends on 7)

The data processing system according to claim 7, wherein mathematical algorithms are stored in a section of the magnetic random access memory that is converted to a read only memory.

### Claim 9 (depends on 4)

The data processing system according to claim 4, wherein the processing unit is a microprocessor or a micro-controller.

### Claim 10 (depends on 9)

The data processing system according to claim 9, wherein customer specific data are stored in a section of the magnetic random access memory that is converted to a read only memory.

### Claim 11 (depends on 9)

The data processing system according to claim 9, wherein secure boot features are stored in a section of the magnetic random access memory that is converted to a read only memory.

### Claim 12

A magnetic random access memory device, comprising:
a magnetic random access memory comprising a first section and a second section, wherein the first section is configured as a read/write memory and the second section is configured as a read only memory, the second section having stored customer specific data or code, and
a conversion circuitry configured to convert at least a part of the first section of the magnet random access memory to a read only memory.