# US 8,570,796 B2 · Nonvolatile memory cell, nonvolatile memory device and method for driving the same

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- Number: US 8,570,796 B2
- Document ID: US8570796B2
- Status: Granted
- Kind: B2
- Application number: 13/619,672
- Filed: 2012-09-14
- Published: 2013-02-14
- Granted: 2013-10-29
- Earliest claimed: 2009-05-19
- Assignees: Hynix Semiconductor Inc.
- Applicants: Hae-Chan Park; Gap-Sok Do; Jang-Uk Lee
- Inventors: Hae-Chan Park; Gap-Sok Do; Jang-Uk Lee
- Web page: https://patentgrep.com/patent/US8570796B2

## CPC

- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/003: {Cell access}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/82: {the switching components having a common active material layer}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8613: {Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.

## Claims

### Claim 1

A nonvolatile memory device, comprising:
a channel line formed of a phase-change material; and
a plurality of first word lines and a plurality of second word lines that are formed on a channel line to face each other across the channel line and control a current flowing through the channel line by each word line being arranged to induce the phase transition in surrounding regions of the channel line independently of other word lines, wherein the first and second word lines are formed on the channel line in the surrounding regions.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first word lines are formed on one side of the channel line and are each arranged to change a crystalline state of a first surrounding region of the channel line using heat generated by a current supplied thereto so that the first surrounding region has a high or low resistance characteristic, wherein the first word lines are formed on the first surrounding region of the channel line.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, wherein the second word lines are formed on the other side of the channel line and are arranged to change a crystalline state of a second surrounding region of the channel line using heat generated by a current supplied thereto so that the second surrounding region has a high or low resistance characteristic, wherein the second word lines are formed on the second surrounding region of the channel line.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, further comprising:
a bit line;
a common source line;
a first switching element connecting the bit line with a first end of the channel line; and
a second switching element connecting the common source line with a second end of the channel line.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein the first and second switching elements are constructed of transistors.

### Claim 6 (depends on 4)

The nonvolatile memory device of claim 4, further comprising a page buffer configured to detect a current flowing through the channel line from the bit line, wherein the channel line is connected to the bit line through the first switching element.

### Claim 7 (depends on 6)

The nonvolatile memory device of claim 6, wherein the page buffer is connected to two bit lines that neighbor each other.

### Claim 8 (depends on 4)

The nonvolatile memory device of claim 4, wherein the bit line is disposed in a direction running parallel with the channel line.

### Claim 9 (depends on 4)

The nonvolatile memory device of claim 4, wherein the common source line is disposed perpendicular to the bit line and connected to a ground terminal.

### Claim 10 (depends on 4)

The nonvolatile memory device of claim 4, wherein the common source line is connected to a plurality of channel lines through a plurality of second switching elements.

### Claim 11 (depends on 4)

The nonvolatile memory device of claim 4, further comprising a first and a second row decoder configured to supply a reset current or a set current to the first and second word lines.

### Claim 12

A method for driving a nonvolatile memory device, the method comprising:
a data writing step of writing data by supplying a reset current or a set current to a selected first word line;
a pre-readout step of supplying the reset current to a second word line facing to the selected first word line; and
a readout step of reading out the data by supplying a readout current to a bit line connected to a channel line.

### Claim 13 (depends on 12)

The method of claim 12, after the readout step, further comprising a post-readout step of supplying the set current to the second word line.

### Claim 14 (depends on 13)

The method of claim 13, wherein, in the post-readout step, a surrounding region of the channel line that is in contact with the second word line is changed from a polycrystalline state to an amorphous state.

### Claim 15 (depends on 13)

The method of claim 13, wherein, in the data writing step, the pre-readout step and the post-readout step, a ground voltage is supplied to the channel line.

### Claim 16 (depends on 12)

The method of claim 12, wherein, in the data writing step, data having a logic value ‘1’ is written in case where the reset current is supplied.

### Claim 17 (depends on 12)

The method of claim 12, wherein, in the data writing step, data having a logic value ‘0’ is written in case where the set current is supplied.

### Claim 18 (depends on 12)

The method of claim 12, wherein, in the data writing step, a surrounding region of the channel line that is in contact with the first word line is changed from a polycrystalline state to an amorphous state in case where the reset current is supplied.

### Claim 19 (depends on 12)

The method of claim 12, wherein, in the data writing step, a surrounding region of the channel line that is in contact with the first word line is changed to a polycrystalline state in case where the set current is supplied.

### Claim 20 (depends on 12)

The method of claim 12, wherein, in the pre-readout step, a surrounding region of the channel line that is in contact with the second word line is changed from a polycrystalline state to an amorphous state in case where the reset current is supplied.