# US 8,570,795 B2 · Adaptive wordline programming bias of a phase change memory

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- Number: US 8,570,795 B2
- Document ID: US8570795B2
- Status: Granted
- Kind: B2
- Application number: 13/535,623
- Filed: 2012-06-28
- Published: 2012-10-25
- Granted: 2013-10-29
- Earliest claimed: 2007-09-18
- Assignees: Intel Corporation
- Applicants: Richard E. Fackenthal; Ferdinando Bedeschi; Meenatchi Jagasivamani; Ravi Annavajjhala; Enzo M. Donze
- Inventors: Richard E. Fackenthal; Ferdinando Bedeschi; Meenatchi Jagasivamani; Ravi Annavajjhala; Enzo M. Donze
- Web page: https://patentgrep.com/patent/US8570795B2

## CPC

- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0071: {Write using write potential applied to access device gate}
- G11C 2213/79: Array wherein the access device being a transistor
- Y10S 977/754: Dendrimer, i.e. serially branching or "tree-like" structure
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

## Claims

### Claim 1

A system comprising:
a processor;
a wireless interface coupled to said processor; and
a phase change memory coupled to said processor, said phase change memory including an array of phase change memory cells and a controller to cause a word line programming voltage of an unselected phase change memory cell to move in the same direction as a programming voltage applied to the bitline of a selected phase change memory cell.

### Claim 2 (depends on 1)

The system of claim 1, said controller to program with a first lower voltage and debias an unselected word line with said first lower voltage.

### Claim 3 (depends on 2)

The system of claim 2, said controller to program with a first higher voltage, higher than said first lower voltage, if the cell is not programmed by said first lower voltage.

### Claim 4 (depends on 3)

The system of claim 3, said controller to use the second higher voltage, higher than the first higher voltage, to program a cell not programmed by a said first higher voltage.

### Claim 5 (depends on 1)

The system of claim 1 including a digital-to-analog converter and a resistor array, said digital-to-analog converter to apply different word line debiasing voltages.

### Claim 6

A system comprising:
a processor;
a wireless interface coupled to said processor; and
a phase change memory coupled to said processor, said phase change memory including an array of phase change memory cells and a controller to cause a word line programming voltage of an unselected phase change memory cell to match a programming voltage applied to the bitline of a selected phase change memory cell; and
a digital-to-analog converter and a resistor array, said digital-to-analog converter to apply different word line debiasing voltages.