# US 8,570,794 B2 · Semiconductor memory apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,794 B2 - Document ID: US8570794B2 - Status: Granted - Kind: B2 - Application number: 12/982,961 - Filed: 2010-12-31 - Published: 2011-10-27 - Granted: 2013-10-29 - Earliest claimed: 2010-04-26 - Assignees: SK hynix Inc. - Applicants: Yong Bok An - Inventors: Yong Bok An - Web page: https://patentgrep.com/patent/US8570794B2 ## CPC - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0061: {Timing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/0078: {Write using current through the cell} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory apparatus includes a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal, a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal, a second write control code generation unit configured to generate a second write control code in response to the programming enable signal, and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code. ## Claims ### Claim 1 A semiconductor memory apparatus comprising: a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal; a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal; a second write control code generation unit configured to generate a second write control code in response to the programming enable signal; and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code. ### Claim 2 (depends on 1) The semiconductor memory apparatus according to claim 1, wherein the first write control codes are cyclically updated for a time longer than an activation time of the second write control code. ### Claim 3 (depends on 1) The semiconductor memory apparatus according to claim 1, wherein the first programming current pulse maintains a current value for the first time, and gradually decreases in current value for the second time after the first time. ### Claim 4 (depends on 1) The semiconductor memory apparatus according to claim 1, wherein the period control signal generation unit comprises: an input latch section configured to output a count enable signal and a reset signal in response to the programming enable signal and a reset pulse signal; a clock generation section configured to generate a clock signal in response to the count enable signal; a counter section configured to output counting codes which are counted under the control of the count enable signal, the reset signal and the clock signal; a comparison section configured to activate and output the period control signal when the counting codes reach a predetermined value; and a latch reset pulse generation section configured to delay the period control signal and output the latch reset pulse signal. ### Claim 5 (depends on 1) The semiconductor memory apparatus according to claim 1, wherein the data write unit comprises: a current control section configured to control a current according to a code combination of the first write control codes and the second write control code; and a current driving section configured to drive the first programming current pulse or the second programming current pulse, with a magnitude corresponding to the current. ### Claim 6 (depends on 5) The semiconductor memory apparatus according to claim 5, wherein the data write unit further comprises: a selection section configured to output the programming current pulse driven from the current driving section to bit lines which respectively correspond to a plurality of select signals. ### Claim 7 A semiconductor memory apparatus comprising: a configuration code output unit configured to output configuration codes; a period control signal generation unit configured to generate a period control signal which is activated after a first time corresponding to the configuration codes, in response to a programming enable signal; a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal; a second write control code generation unit configured to generate a second write control code in response to the programming enable signal; and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code. ### Claim 8 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the first write control codes are cyclically updated for a time longer than an activation time of the second write control code. ### Claim 9 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the first programming current pulse maintains a current value for the first time, and gradually decreases in current value for the second time after the first time. ### Claim 10 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the period control signal generation unit comprises: an input latch section configured to output a count enable signal and a reset signal in response to the programming enable signal and a reset pulse signal; a clock generation section configured to generate a clock signal in response to the count enable signal; a counter section configured to output counting codes which are counted under the control of the count enable signal, the reset signal and the clock signal; a comparison section configured to compare the counting codes and the configuration codes, and activate and output the period control signal according to a comparison result; and a latch reset pulse generation section configured to delay the period control signal and output the latch reset pulse signal. ### Claim 11 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the data write unit comprises: a current control section configured to control a current according to a code combination of the first write control codes and the second write control code; and a current driving section configured to drive the first programming current pulse or the second programming current pulse, with a magnitude corresponding to the current. ### Claim 12 (depends on 11) The semiconductor memory apparatus according to claim 11, wherein the data write unit further comprises: a selection section configured to output the programming current pulse driven from the current driving section to bit lines which respectively correspond to a plurality of select signals. ### Claim 13 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the configuration code output unit comprises: a latch section configured to store the configuration codes. ### Claim 14 (depends on 7) The semiconductor memory apparatus according to claim 7, wherein the configuration codes are signals which are outputted from a mode register set. ### Claim 15 A semiconductor memory apparatus comprising: a data write unit configured to output a first programming current which has a first period of supplying the largest first programming current, and a second period of supplying a decreasing first programming current; a period control signal generation unit configured to generate a period control signal which control a duration of the first period; a first write control code generation unit configured to generate a first programming control code which control the first programming current; and a configuration code output unit configured to output a configuration code to be compared with an internal code of the period control signal generation unit. ### Claim 16 (depends on 15) The semiconductor memory apparatus according to claim 15, wherein the internal code of the period control signal generation unit is an output of a counter logic in the period control signal generation unit.