# US 8,570,791 B2 · Circuit and method of word line suppression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,791 B2 - Document ID: US8570791B2 - Status: Granted - Kind: B2 - Application number: 13/253,110 - Filed: 2011-10-05 - Published: 2013-04-11 - Granted: 2013-10-29 - Earliest claimed: 2011-10-05 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Jack Liu - Inventors: Jack Liu - Web page: https://patentgrep.com/patent/US8570791B2 ## CPC - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage. ## Claims ### Claim 1 A word line driver circuit for providing a suppressed word line voltage comprising: a switch configured to selectively couple a word line to a suppressed word line voltage node; and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node, the word line charging circuit comprising a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage. ### Claim 2 (depends on 1) The word line driver circuit of claim 1, wherein the switch comprises a CMOS inverter coupled between the suppressed word line voltage node and a ground node. ### Claim 3 (depends on 1) The word line driver circuit of claim 1, wherein the control pulse has a pulse length such that the first transistor device is turned off before the suppressed word line voltage node reaches a voltage of the high power supply node. ### Claim 4 (depends on 3) The word line driver circuit of claim 3, further comprising a control pulse generation circuit, the control pulse generation circuit including a delay element for providing a delay corresponding to the pulse length of the control pulse. ### Claim 5 (depends on 1) The word line driver circuit of claim 1, wherein the first transistor device is a PMOS transistor having a source terminal coupled to the high power supply node, a drain terminal coupled to the suppressed word line voltage node and a gate terminal to which the control pulse is coupled. ### Claim 6 (depends on 5) The word line driver circuit of claim 5, wherein the second transistor device is a diode connected PMOS transistor. ### Claim 7 (depends on 6) The word line driver circuit of claim 6, wherein the diode connected PMOS transistor has a source terminal coupled to the high power supply node and drain and gate terminals coupled to the suppressed word line voltage node. ### Claim 8 (depends on 5) The word line driver circuit of claim 5, wherein the second transistor device is a PMOS transistor having a drive capability lower than a drive capability of the first transistor device. ### Claim 9 (depends on 8) The word line driver circuit of claim 8, wherein the second transistor device is smaller than the first transistor device. ### Claim 10 A method of generating a suppressed word line voltage comprising the steps of: coupling a word line to a suppressed word line voltage node; charging the suppressed word line voltage node to a suppressed word line voltage with a first transistor device; after the word line voltage node reaches the suppressed word line voltage, turning the first transistor device off; and after turning the first transistor device off, maintaining the suppressed word line voltage node at the suppressed word line voltage, using a second transistor device. ### Claim 11 (depends on 10) The method of claim 10, further comprising the step of providing a control pulse for controlling the first transistor device. ### Claim 12 (depends on 11) The method of claim 11, wherein the control pulse has a pulse length such that the first transistor device is turned off before the suppressed word line voltage node reaches a voltage of a high power supply node to which the first transistor device is connected. ### Claim 13 (depends on 10) The method of claim 10, wherein the second transistor device is a diode connected PMOS transistor. ### Claim 14 (depends on 10) The method of claim 10, wherein the second transistor device has a drive capability lower than a drive capability of the first transistor device. ### Claim 15 A static random access memory (SRAM) comprising: a first bit cell of a static random access memory (SRAM) including cross coupled inverters configured for storing and retrieving a logic state; a word line coupled to the first bit cell wherein the first bit cell is accessible via bit line connections through a passing gate transistor of the first bit cell controlled by the word line; a word line driver circuit configured to provide a word line signal at the word line to drive the first bit cell during a memory access cycle, the word line driver circuit comprising: a switch configured to selectively couple the word line to a suppressed word line voltage node; and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node, the word line charging circuit comprising a first transistor device responsive to a control, pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage. ### Claim 16 (depends on 15) The SRAM of claim 15, wherein the control pulse has a pulse length such that the first transistor device is turned off before the suppressed word line voltage node reaches a voltage of the high power supply node. ### Claim 17 (depends on 16) The SRAM of claim 16, further comprising a control pulse generation circuit, the control pulse generation circuit including a delay element for providing a delay corresponding to the pulse length of the control pulse. ### Claim 18 (depends on 16) The SRAM of claim 16, wherein: the first transistor device is a PMOS transistor having a source terminal coupled to the high power supply node, a drain terminal coupled to the suppressed word line voltage node and to gate terminal to which the control pulse is coupled; and the second transistor device is a diode connected PMOS transistor having a source terminal coupled to the high power supply node and drain and gate terminals coupled to the suppressed word line voltage node. ### Claim 19 (depends on 16) The SRAM of claim 16, wherein: the first transistor device is a PMOS transistor having a source terminal coupled to the high power supply node, a drain terminal coupled to the suppressed word line voltage node and a gate terminal to which the control pulse is coupled; and wherein the second transistor device is a PMOS transistor having a drive capability lower than a drive capability of the first transistor device. ### Claim 20 (depends on 15) The SRAM of claim 15, wherein the switch comprises a CMOS inverter coupled between the suppressed word line voltage node and a ground node.