# US 8,570,786 B2 · Memory device and fabricating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,786 B2 - Document ID: US8570786B2 - Status: Granted - Kind: B2 - Application number: 13/177,857 - Filed: 2011-07-07 - Published: 2013-01-10 - Granted: 2013-10-29 - Earliest claimed: 2011-07-07 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kenichi Murooka - Inventors: Kenichi Murooka - Web page: https://patentgrep.com/patent/US8570786B2 ## CPC - H10N 70/821: {Device geometry} - G11C 13/0002: {using resistive RAM [RRAM] elements} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10N 70/068: {by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers} - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels} - G11C 2213/71: Three dimensional array - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion. ## Claims ### Claim 1 A memory device comprising: a plurality of first interconnects located in parallel; a plurality of second interconnects located in parallel; and a first memory cell located in an intersection of one of the first interconnects and one of the second interconnects, wherein the first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked, the first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect, and the first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion. ### Claim 2 (depends on 1) The device according to claim 1, wherein the second interconnects are positioned higher than the first interconnects, the first variable resistance layer is formed on a first side surface pair of the first multilayer structure without being formed on a second side surface pair, the first side surface pair including side surfaces facing each other in a direction along the first interconnects, the second side surface pair including side surfaces facing each other in a direction along the second interconnects. ### Claim 3 (depends on 1) The device according to claim 1, wherein the second interconnects are positioned higher than the first interconnects, the first variable resistance layer is formed on a first side surface pair of the first multilayer structure without being formed on a second side surface pair, the first side surface pair including side surfaces facing each other in a direction along the second interconnects, the second side surface pair including side surfaces facing each other in a direction along the first interconnects. ### Claim 4 (depends on 1) The device according to claim 1, further comprising: a plurality of third interconnects located in parallel, the third interconnects being in parallel with the first interconnects; and a second memory cell located in an intersection of the one of the second interconnects and one of the third interconnects, wherein the second memory cell includes a second multilayer structure and a second variable resistance layer, the second multilayer structure including a second electrode, a second selector, and a second insulator which are stacked, the second selector and the second variable resistance layer are electrically connected in series between the one of the second interconnects and the one of the third interconnects, and the second variable resistance layer is formed on a portion of a side surface of the second insulator to cover the portion without covering a residual portion. ### Claim 5 (depends on 4) The device according to claim 4, wherein the first variable resistance layer is formed on a first side surface pair of the first multilayer structure without being formed on a second side surface pair, the second variable resistance layer is formed on a second side surface pair of the second multilayer structure without being formed on a first side surface pair, the first side surface pairs of the first and second multilayer structures including side surfaces facing each other in one of a first direction and a second direction, the first direction being along the first and third interconnects, the second direction being along the second interconnects, and the second side surface pairs of the first and second multilayer structures including side surfaces facing each other in another direction. ### Claim 6 (depends on 1) The device according to claim 1, wherein a breakdown voltage of the first insulator with respective to a stacking direction is higher than a voltage required to change a resistance state of the first variable resistance layer. ### Claim 7 (depends on 1) The device according to claim 1, wherein the first variable resistance layer is formed by atomic layer deposition. ### Claim 8 (depends on 1) The device according to claim 1, further comprising: a first selection unit configured to select one of the first interconnects; a second selection unit configured to select one of the second interconnects; a first driver configured to apply a first voltage and a second voltage to selected one of the first interconnects and unselected one of the first interconnects; a second driver configured to apply a third voltage and a fourth voltage to selected one of the second interconnects and unselected one of the second interconnects; and a controller configured to control a data writing operation into the first memory cell and a data reading operation from the first memory cell, the controller setting the first to fourth voltages to voltages for data writing to change a resistance of the variable resistance layer of the selected first memory cell in the data writing operation, the controller setting the first to fourth voltages to voltages for data reading to detect a resistance, as the memory state, of the variable resistance layer of the selected first memory cell in the data read operation. ### Claim 9 (depends on 1) The device according to claim 1, wherein the first multilayer structure includes a second electrode, the first insulator, a third electrode, the first selector, and the first electrode which are sequentially stacked, the first electrode is contacted with the one of the second interconnects, and the first variable resistance layer is continuously formed between the second electrode and the third electrode. ### Claim 10 (depends on 1) The device according to claim 1, wherein the first multilayer structure includes a second electrode, the first insulator, a third electrode, the first selector, and the first electrode which are sequentially stacked, the third electrode is contacted with the one of the second interconnects, and the first variable resistance layer is continuously formed between the second electrode and the third electrode.