# US 8,570,785 B2 · Reading a memory element within a crossbar array

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,570,785 B2
- Document ID: US8570785B2
- Status: Granted
- Kind: B2
- Application number: 12/788,161
- Filed: 2010-05-26
- Published: 2011-12-01
- Granted: 2013-10-29
- Earliest claimed: 2010-05-26
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Frederick Perner
- Inventors: Frederick Perner
- Web page: https://patentgrep.com/patent/US8570785B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2211/5645: Multilevel memory with current-mirror arrangements
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

## Claims

### Claim 1

A system for reading memory, elements within a crossbar array, said crossbar array comprising a set of row lines intersecting a set of column lines, memory elements being disposed at intersections between said row lines and said column lines, the system comprising:
a current mirror, an input of said current mirror being selectively connected through switching circuitry to a column line of said set of column lines;
an error voltage supply selectively connected through additional switching circuitry to said row lines, wherein an error voltage produced by said error voltage supply is matched to a voltage formed across said current mirror; and
a sense voltage supply for selectively applying a sense voltage to one of said row lines;
in which said sense voltage and said error voltage create an output current of said current mirror.

### Claim 2 (depends on 1)

The system of claim 1, in which said output current corresponds to a resistive state of a target memory element connected to said column line and said one of said row lines having said sense voltage applied.

### Claim 3 (depends on 2)

The system of claim 2, in which said sense voltage is designed so that an electric current flowing through said target memory element is substantially larger than a total electric current flowing through half-selected memory elements within said crossbar array.

### Claim 4 (depends on 1)

The system of claim 1, in which said current mirror is configured to scale said output current.

### Claim 5 (depends on 4)

The system of claim 4, in which said current mirror is configured to scale said output current to accommodate sensing circuitry receiving said output current of said current mirror.

### Claim 6 (depends on 1)

The system of claim 1, in which said crossbar array is a disjointed crossbar array.

### Claim 7 (depends on 1)

The system of claim 1, in which memory elements within said crossbar array comprise non-linear resistive elements.

### Claim 8 (depends on 7)

The system of claim 7, in which said non-linear resistive memory elements within said crossbar array comprise memristive elements.

### Claim 9 (depends on 1)

The system of claim 1, wherein said switching circuitry connects a column line, which is connected to a target memory element, to said current mirror, wherein said target memory element is further connected to a row line that, during operation of said system, receives said sense voltage from said sense voltage supply.