# US 8,570,784 B2 · Differential ROM > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,784 B2 - Document ID: US8570784B2 - Status: Granted - Kind: B2 - Application number: 13/192,702 - Filed: 2011-07-28 - Published: 2013-01-31 - Granted: 2013-10-29 - Earliest claimed: 2011-07-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Jack Liu - Inventors: Jack Liu - Web page: https://patentgrep.com/patent/US8570784B2 ## CPC - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/08: Control thereof - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 17/12: using field-effect devices - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A differential read only memory array includes a differential sense amplifier coupled to first and second bit lines. A first bit cell is coupled to a first word line and to the first and second bit lines. The at least one bit cell includes a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line. A second transistor has a gate coupled to the first word line. A source and a drain of the second transistor are either both connected to the second bit line or both unconnected to the second bit line. ## Claims ### Claim 1 A differential read only memory array, comprising: a differential sense amplifier coupled to first and second bit lines; and at least one bit cell coupled to a first word line and to the first and second bit lines, the at least one bit cell including: a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line; and a second transistor having a gate coupled to the first word line, wherein a source and a drain of the second transistor are directly coupled together and to the second bit line such that the source and drain are not directly connected to a power supply line. ### Claim 2 (depends on 1) The differential read only memory array of claim 1, further comprising a second bit cell coupled to the first word line and to third and fourth bit lines, the second bit cell including: a third transistor having a gate coupled to the first word line, a drain coupled to the third bit line, and a source coupled to the first power supply line; and a fourth transistor having a gate coupled to the first word line and a drain and a source coupled to the fourth bit line. ### Claim 3 (depends on 1) The differential read only memory array of claim 1, further comprising a second bit cell coupled to a second word line and to the first and second bit lines, the second bit cell including: a third transistor having a gate coupled to the second word line, a drain coupled to the first bit line, and a source coupled to the first power supply line; and a fourth transistor having a gate coupled to the second word line and a drain and a source coupled to the second bit line. ### Claim 4 (depends on 1) The differential read only memory array of claim 1, further comprising a second bit cell coupled to a second word line and to the third and fourth bit lines, the second bit cell including: a third transistor having a gate coupled to the second word line and a source and a drain coupled to the first bit line; and a fourth transistor having a gate coupled to the second word line, a drain coupled to the second bit line, and a source coupled to the first power supply line. ### Claim 5 (depends on 1) The differential read only memory array of claim 1, wherein the second transistor has its drain and source decoupled from the first and second bit line lines. ### Claim 6 (depends on 5) The differential read only memory array of claim 5, further comprising a second bit cell coupled to the first word line and to third and fourth bit lines, the second bit cell including: a third transistor having a gate coupled to the first word line, a drain coupled to the third bit line, and a source coupled to the first power supply line; and a fourth transistor having a gate coupled to the first word line and a drain and a source that are unconnected to the fourth bit line. ### Claim 7 (depends on 5) The differential read only memory array of claim 5, further comprising a second bit cell coupled to a second word line and to the first and second bit lines, the second bit cell including: a third transistor having a gate coupled to the second word line, a drain coupled to the first bit line, and a source coupled to the first power supply line; and a fourth transistor having a gate coupled to the second word line and a drain and a source unconnected to the second bit line. ### Claim 8 (depends on 5) The differential read only memory array of claim 5, further comprising a second bit cell coupled to a second word line and to the first and second bit lines, the second bit cell including: a third transistor having a gate coupled to the second word line and a drain and a source unconnected to the first bit line; and a fourth transistor having a gate coupled to the second word line, a drain coupled to the second bit line, and a source coupled to the first power supply line. ### Claim 9 A semiconductor memory, comprising: a plurality of differential sense amplifiers each coupled to a respective pair of bit lines; and a plurality of differential read only bit cells arranged in a plurality of rows and a plurality of columns, each of the plurality of rows associated with a respective word line, and each of the plurality of columns associated with a respective pair of bit lines, wherein a first bit cell is disposed in a first row and includes: a first transistor having a gate coupled to a first word line, a source coupled to a first power supply, and a drain coupled to the first bit line, wherein the first bit cell is configured to output a logic zero to the first bit line, a second transistor has a gate coupled to the first word line, and a source and a drain of the second transistor are both directly connected to the second bit line such that the source and drain are not directly connected to a power supply line. ### Claim 10 (depends on 9) The semiconductor memory of claim 9, wherein the first row includes a second bit cell comprising: a third transistor having a gate coupled to the first word line, a source coupled to the first power supply, and a drain coupled to the third bit line; and a fourth transistor having a gate coupled to the first word line and a source and a drain coupled to a fourth bit line. ### Claim 11 (depends on 9) The semiconductor memory of claim 9, wherein the first bit cell and a second bit cell are disposed in a first column, the second bit cell configured to output a logic zero to the first bit line during a read operation and includes: a third transistor having a gate coupled to a second word line, a source coupled to the first power supply, and a drain coupled to the first bit line; and a fourth transistor having a gate coupled to the second word line and a source and a drain coupled to the second bit line. ### Claim 12 (depends on 9) The semiconductor memory of claim 9, wherein the first bit cell and a second bit cell are disposed in a first column, the second bit cell configured to output a logic one to the first bit line during a read operation and includes: a third transistor having a gate coupled to a second word line and a source and a drain coupled to the first bit line; and a fourth transistor having a gate coupled to the second word line, a source coupled to the first power supply, and a drain coupled to a second bit line. ### Claim 13 (depends on 9) The semiconductor memory of claim 9, wherein the first bit cell is configured to output a logic zero to a first bit line, and the source and the drain are unconnected to the second bit line. ### Claim 14 (depends on 13) The semiconductor memory of claim 13, wherein the first row includes a second bit cell disposed between third and fourth bit lines, the second bit cell comprising: a third transistor having a gate coupled to the first word line, a source coupled to the first power supply, and a drain coupled to the third bit line; and a fourth transistor having a gate coupled to the first word line and a source and a drain unconnected to a fourth bit line. ### Claim 15 (depends on 13) The semiconductor memory of claim 13, wherein the first bit cell and a second bit cell are disposed in a first column, the second bit cell configured to output a logic one to the first bit line during a read operation and includes: a third transistor having a gate coupled to a second word line, a source coupled to the first power supply, and a drain coupled to the second bit line; and a fourth transistor having a gate coupled to the second word line and a source and a drain unconnected to the first bit line. ### Claim 16 (depends on 13) The semiconductor memory of claim 13, wherein the first bit cell and a second bit cell are disposed a first column, the second bit cell configured to output a logic zero to the first bit line during a read operation and includes: a third transistor having a gate coupled to a second word line, a source coupled to the first power supply, and a drain coupled to the first bit line; and a fourth transistor having a gate coupled to the second word line and a source and a drain unconnected to the second bit line. ### Claim 17 (depends on 9) The semiconductor memory of claim 9, wherein the first bit cell is configured to output a logic one to the second bit line, the source and the drain of the second transistor are coupled to the first bit line. ### Claim 18 (depends on 9) The semiconductor memory of claim 9, wherein the first bit cell is configured to output a logic one to the second bit line, and the source and the drain of the second transistor are unconnected to the first bit line.