# US 8,570,709 B2 · Ceramic electronic component, method of manufacturing the same, and collective component > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,709 B2 - Document ID: US8570709B2 - Status: Granted - Kind: B2 - Application number: 12/892,994 - Filed: 2010-09-29 - Published: 2011-05-05 - Granted: 2013-10-29 - Earliest claimed: 2009-10-29 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Hiroto Itamura - Inventors: Hiroto Itamura - Web page: https://patentgrep.com/patent/US8570709B2 ## CPC - H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)} - H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor - H01G 4/30: Stacked capacitors (H01G4/33 takes precedence) - Y10T 29/435: Solid dielectric type - Y10T 29/49002: Electrical device making - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A collective component has a first region that intersects with a conductive film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect with the conductive film for external terminal electrodes in the break line. The plurality of break leading holes includes at least one extending break leading hole located so as to extend over the first region and the second region. ## Claims ### Claim 1 A ceramic electronic component comprising: a ceramic element assembly that has mutually opposite first and second principal surfaces and first to fourth side surfaces that connect the first and second principal surfaces; and an external conductor on the first principal surface of the ceramic element assembly, wherein a plurality of recessed grooves on the first side surface which extend in a direction to connect the first and second principal surfaces and at least reach the first principal surface, wherein a first edge portion of the first principal surface, which contacts the first side surface, has at least two first regions in which an edge of the external conductor is located, and at least one second region which is located between two adjacent first regions and in which the edge of the external conductor is not located, and wherein the plurality of recessed grooves include at least one extending recessed groove disposed so as to extend over the adjacent first regions and the second region therebetween, wherein the external conductor comprises a first external conductor having an edge located in one of the at least two first regions and a second external conductor having an edge located in the other one of the at least two first regions, and wherein the first external conductor and the second external conductor on the first principal surface are independent of each other, wherein the ceramic electronic component constitutes a monolithic ceramic capacitor that includes a plurality of laminated dielectric layers and first and second internal electrodes that face each other across a dielectric layer, wherein the first external conductor is electrically connected to the first internal electrode, and wherein the second external conductor is electrically connected to the second internal electrode. ### Claim 2 (depends on 1) The ceramic electronic component according to claim 1, wherein the adjacent recessed grooves partially overlap each other in the second region. ### Claim 3 (depends on 1) The ceramic electronic component according to claim 1, wherein the adjacent recessed grooves are independent of each other in the second region. ### Claim 4 (depends on 1) The ceramic electronic component according to claim 1, wherein the dielectric layers and the first and second internal electrodes extend vertically with respect to the first principal surface. ### Claim 5 (depends on 1) The ceramic electronic component according to claim 1, wherein the dielectric layers and the first and second internal electrodes extend parallel to the first principal surface, wherein the first external conductor is electrically connected to the first internal electrode by a first via conductor, and wherein the second external conductor is electrically connected to the second internal electrode by a second via conductor. ### Claim 6 (depends on 1) The ceramic electronic component according to claim 1, wherein the recessed grooves are arranged at a constant pitch. ### Claim 7 (depends on 1) The ceramic electronic component according to claim 1, having an external conductor on the second principal surface. ### Claim 8 (depends on 1) The ceramic electronic component according to claim 1, wherein a second edge portion of the first principal surface which contacts the second side surface facing the first side surface has a similar configuration to the first edge portion. ### Claim 9 (depends on 1) The ceramic electronic component according to claim 1, wherein a surface of the external conductor is Cu. ### Claim 10 A ceramic electronic component comprising: a ceramic element assembly that has mutually opposite first and second principal surfaces and first to fourth side surfaces that connect the first and second principal surfaces; and an external conductor having a Cu surface on the first principal surface of the ceramic element assembly, wherein a plurality of recessed grooves on the first side surface which extend in a direction to connect the first and second principal surfaces and at least reach the first principal surface, wherein a first edge portion of the first principal surface, which contacts the first side surface, has at least two first regions in which an edge of the external conductor is located, and at least one second region which is located between two adjacent first regions and in which the edge of the external conductor is not located, and wherein the plurality of recessed grooves include at least one extending recessed groove disposed so as to extend over the adjacent first regions and the second region therebetween, wherein the extending recessed groove comprises interconnected grooves, a first of which is disposed so as to extend over the first region and a second of which is disposed so as to extend over the second region, wherein the pitch P2 between the first and second interconnected groves is smaller than the pitch P1 between adjacent recessed groves. ### Claim 11 (depends on 10) The ceramic electronic component according to claim 10, wherein the pitch P3 between the recessed grove and the adjacent groove extending over a first or second region is less than or equal to P1. ### Claim 12 (depends on 11) The ceramic electronic component according to claim 11, wherein P1 is about 150 to 250 μm, P2 is about 40 to 60 μm, pitch P3 is about 150 to 250 μm, the length of each recessed grove is about 80 to 120 μm, and the length of the extending recessed grove is about 160 to 240 μm. ### Claim 13 (depends on 12) The ceramic electronic component according to claim 12, wherein the ceramic electronic component is a monolithic ceramic capacitor that includes a plurality of laminated dielectric layers and first and second internal electrodes that face each other across a dielectric layer, the external conductor comprises a first external conductor having an edge located in one of the at least two first regions and a second external conductor having an edge located in the other one of the at least two first regions, the first external conductor is electrically connected to the first internal electrode, and the second external conductor is electrically connected to the second internal electrode, wherein the distance between the first and second principle surfaces is about 0.3 to 1.5 mm, the thickness of each internal electrode and dielectric layer is about 1 to 10 μm, and wherein the first and second external conductors comprise an about 5 to 40 μm thick electrically conductive base layer having at least one about 1 to 10 μm thick electrically conductive plating layer thereon.