# US 8,570,707 B2 · Scalable integrated circuit high density capacitors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,570,707 B2
- Document ID: US8570707B2
- Status: Granted
- Kind: B2
- Application number: 13/162,257
- Filed: 2011-06-16
- Published: 2012-01-26
- Granted: 2013-10-29
- Earliest claimed: 2003-12-19
- Assignees: Broadcom Corporation
- Applicants: Victor Chiu-Kit Fong; Eric Bruce Blecker; Tom W. Kwan; Ning Li; Sumant Rangnathan; Chao Tang; Pieter Vorenkamp
- Inventors: Victor Chiu-Kit Fong; Eric Bruce Blecker; Tom W. Kwan; Ning Li; Sumant Rangnathan; Chao Tang; Pieter Vorenkamp
- Web page: https://patentgrep.com/patent/US8570707B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/692: {Electrodes}
- H10D 84/212: {of only capacitors}
- H10W 20/423: {Shielding layers}
- H10D 89/10: Integrated device layouts
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

## Claims

### Claim 1

A capacitor, comprising:
a plurality of metal layers; and
a first metallization pattern and a second metallization pattern disposed on respective metal layers of the plurality of metal layers, each metallization pattern including an interdigitated finger track approximately perpendicular to a respective backbone track, wherein
the interdigitated finger track in the first metallization pattern is offset with respect to the interdigitated finger track in the second metallization pattern.

### Claim 2 (depends on 1)

The capacitor of claim 1, wherein the first metallization pattern is electrically coupled to the second metallization pattern.

### Claim 3 (depends on 1)

The capacitor of claim 1 , wherein a portion of the interdigitated finger track in the first metallization pattern overlaps a portion of the interdigitated finger track in the second metallization pattern.

### Claim 4 (depends on 1)

The capacitor of claim 1, wherein a first central axis of the interdigitated finger track in the first metallization pattern is substantially parallel to a second central axis of the interdigitated finger track in the second metallization pattern.

### Claim 5 (depends on 1)

The capacitor of claim 1, wherein the interdigitated finger track in the first metallization pattern, extending from a non-distal and non-proximal portion of the respective backbone track in the first metallization pattern, partially overlaps the interdigitated finger track in the second metallization pattern.

### Claim 6 (depends on 1)

The capacitor of claim 1, wherein a first shield is disposed on a top-most metal layer of the plurality of metal layers, and a second shield is disposed on a bottom-most metal layer of the plurality of metal layers.

### Claim 7 (depends on 1)

The capacitor of claim 1, wherein at least one of the first metallization pattern and the second metallization pattern is electrically coupled. to reduce parasitic capacitance.

### Claim 8 (depends on 1)

The capacitor claim 1, wherein a width of the interdigitated finger track in the first metallization pattern is larger than a width of the interdigitated finger track in the second metallization pattern.

### Claim 9 (depends on 1)

The capacitor of claim 1, wherein a width of the interdigitated finger track in the first metallization pattern is smaller than a width of the interdigitated finger track in the second metallization pattern.

### Claim 10 (depends on 1)

The capacitor of claim 1, wherein the interdigitated finger track in the first metallization pattern is staggered with respect to the interdigitated finger track in the second metallization pattern.

### Claim 11 (depends on 1)

The capacitor of claim 1, wherein the interdigitated finger track in the first metallization pattern is offset by more than one-half of a width of the interdigitated finger track in the first metallization pattern with respect to the interdigitated finger track in the second metallization pattern.

### Claim 12

A capacitor, comprising:
a plurality of metal layers; and
a first metallization pattern and a second metallization pattern disposed on respective metal layers of the plurality of metal layers, each metallization pattern including an interdigitated finger track approximately perpendicular to a respective backbone track, wherein
the interdigitated finger track in the first metallization pattern is offset by more than one-half of a width of the interdigitated finger track in the first metallization pattern with respect to the interdigitated finger track in the second metallization pattern.

### Claim 13 (depends on 12)

The capacitor of claim 12, wherein the interdigitated finger track in the first metallization pattern, extending from a non-distal and non-proximal portion of the respective backbone track in the first metallization pattern, partially overlaps the interdigitated finger track in the second metallization pattern.

### Claim 14 (depends on 12)

The capacitor of claim 12, wherein a width of the interdigitated finger track in the first metallization pattern is larger than a width of the interdigitated finger track in the second metallization pattern.

### Claim 15 (depends on 12)

The capacitor of claim 12, wherein a width of the interdigitated finger track in the first metallization pattern is smaller than a width of the interdigitated finger track in the second metallization pattern.

### Claim 16 (depends on 12)

The capacitor of claim 12, wherein a first shield is disposed on a top-most metal layer of the plurality of metal layers, and a second shield is disposed on a bottom-most metal layer of the plurality of metal layers.

### Claim 17 (depends on 12)

The capacitor of claim 12, wherein a first central axis of the interdigitated finger track in the first metallization pattern is substantially parallel to a second central axis of the interdigitated finger track in the second metallization pattern.

### Claim 18 (depends on 12)

The capacitor of claim 12, wherein a portion of the interdigitated finger track in the first metallization pattern overlaps a portion of the interdigitated finger track in the second metallization pattern.

### Claim 19 (depends on 12)

The capacitor of claim 12, wherein the interdigitated finger track in the first metallization pattern is offset with respect to the interdigitated finger track in the second metallization pattern.