# US 8,570,453 B2 · Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device and television receiver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,453 B2 - Document ID: US8570453B2 - Status: Granted - Kind: B2 - Application number: 13/146,636 - Filed: 2009-10-29 - Published: 2011-11-17 - Granted: 2013-10-29 - Earliest claimed: 2009-02-03 - Assignees: Sharp Kabushiki Kaisha - Applicants: Toshihide Tsubata - Inventors: Toshihide Tsubata - Web page: https://patentgrep.com/patent/US8570453B2 ## CPC - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G02F 1/13624: {having more than one switching element per pixel} - G09G 3/3614: {Control of polarity reversal in general} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G02F 1/134354: {the sub-pixels being capacitively coupled} - G09G 2320/028: by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract With a configuration in which a first pixel electrode (17a) electrically connected to a first transistor (12) and a second pixel electrode (17b) connected to the first pixel electrode (17a) through a capacitance are provided in a single pixel, a storage capacitance wiring (18j) is formed in the same layer with a data signal line (15j), a second transistor (212c) is electrically connected to the storage capacitance wiring (18j) and to the first pixel electrode (17a), and a third transistor (212b) is electrically connected to the storage capacitance wiring (18j) and to the second pixel electrode (17b), a capacitance coupling type active matrix substrate equipped with transistors for discharge suppresses the aperture ratio reduction and load increase on gate bus lines (scan signal lines). ## Claims ### Claim 1 An active matrix substrate comprising: scan signal lines that extend in a row direction; data signal lines that extend in a column direction, the scan signal lines and the data signal lines intersecting each other and defining a matrix of pixel regions; a first transistor connected to a data signal line and a scan signal line in each of the pixel regions; second and third transistors connected to a same scan signal line that is different from said scan signal line in each of the pixel regions; and a storage capacitance wiring, wherein a first pixel electrode electrically connected to said first transistor and a second pixel electrode connected to said first pixel electrode through a capacitance are provided in each of the pixel regions, wherein said storage capacitance wiring is formed in a same layer with the data signal lines, wherein said second transistor is electrically connected to said storage capacitance wiring and said first pixel electrode in each of the pixel regions, and wherein said third transistor is electrically connected to said storage capacitance wiring and said second pixel electrode in each of the pixel region. ### Claim 2 (depends on 1) The active matrix substrate according to claim 1, wherein said first transistor is connected to a current scan signal line, and said second and third transistors are connected to a previous scan signal line. ### Claim 3 (depends on 2) The active matrix substrate according to claim 2, wherein said second and third transistors are provided near an intersecting portion of said previous scan signal line and said storage capacitance wiring. ### Claim 4 (depends on 1) The active matrix substrate according to claim 1, wherein said storage capacitance wiring extends in the column direction. ### Claim 5 (depends on 1) The active matrix substrate according to claim 1, wherein said storage capacitance wiring overlaps said first and second pixel electrodes through an interlayer insulating film that covers channels of respective transistors. ### Claim 6 (depends on 5) The active matrix substrate according to claim 5, further comprising a first capacitance electrode electrically connected to the first pixel electrode, wherein said first capacitance electrode and said second pixel electrode overlap with each other through an insulating layer. ### Claim 7 (depends on 6) The active matrix substrate according to claim 6, wherein said first capacitance electrode is formed in a same layer with the scan signal lines. ### Claim 8 (depends on 7) The active matrix substrate according to claim 7, wherein said first capacitance electrode and said storage capacitance wiring overlap with each other through a gate insulating film. ### Claim 9 (depends on 7) The active matrix substrate according to claim 7, wherein said first pixel electrode, a drain lead-out electrode led out from the drain electrode of the first transistor, and said first capacitance electrode are connected together by a single contact hole. ### Claim 10 (depends on 8) The active matrix substrate according to claim 8, wherein the first capacitance electrode has two edges that are parallel to each other, the storage capacitance wiring has two edges that are parallel to each other, and the both edges of the storage capacitance wiring fall between the edges of the first capacitance electrode when observed in a plan view. ### Claim 11 (depends on 8) The active matrix substrate according to claim 8, wherein the first capacitance electrode has two edges that are parallel to each other, the storage capacitance wiring has two edges that are parallel to each other, and the both edges of the first capacitance electrode fall between the edges of the storage capacitance wiring when observed in a plan view. ### Claim 12 (depends on 1) The active matrix substrate according to claim 1, wherein the first and the second pixel electrodes are arranged in the column direction. ### Claim 13 (depends on 1) The active matrix substrate according to claim 1, wherein the first and the second pixel electrodes are arranged in the row direction. ### Claim 14 (depends on 1) The active matrix substrate according to claim 1, further comprising a third pixel electrode that is electrically connected to the first pixel electrode. ### Claim 15 (depends on 1) The active matrix substrate according to claim 1, further comprising a second capacitance electrode electrically connected to the second pixel electrode, wherein said second capacitance electrode and said first pixel electrode overlap with each other through an insulating layer. ### Claim 16 (depends on 14) The active matrix substrate according to claim 14, further comprising a second capacitance electrode electrically connected to the second pixel electrode, wherein the second capacitance electrode and the third pixel electrode overlap through an insulating layer. ### Claim 17 (depends on 15) The active matrix substrate according to claim 15, wherein a portion of a drain lead-out electrode led out from the drain electrode of the third transistor functions as said second capacitance electrode. ### Claim 18 (depends on 13) The active matrix substrate according to claim 13, wherein, in one of two pixel regions arranged next to each other in the column direction, the first transistor is connected to one of two adjacent data signal lines, and in the other of said two pixel regions, the first transistor is connected to the other of said two data signal lines. ### Claim 19 (depends on 18) The active matrix substrate according to claim 18, wherein the first pixel electrode provided in one of said two pixel regions and the second pixel electrode provided in another pixel region are adjacent to each other in the column direction. ### Claim 20 (depends on 13) The active matrix substrate according to claim 13, wherein said storage capacitance wiring extends in the column direction and overlaps with the first and the second pixel electrodes and a space between them. ### Claim 21 (depends on 20) The active matrix substrate according to claim 20, further comprising first and second capacitance electrodes in a same layer with the scan signal line, wherein said first capacitance electrode connected to the first pixel electrode through a contact hole crosses under the storage capacitance wiring and arrives under the second pixel electrode, while said second capacitance electrode connected to the second pixel electrode through a contact hole crosses under the storage capacitance wiring and arrives under the first pixel electrode. ### Claim 22 (depends on 21) The active matrix substrate according to claim 21, wherein said first and second capacitance electrodes are formed symmetrically with each other with respect to a point or a line. ### Claim 23 (depends on 1) A liquid crystal panel comprising the active matrix substrate according to claim 1. ### Claim 24 (depends on 23) A liquid crystal display unit comprising the liquid crystal panel according to claim 23 and a driver. ### Claim 25 (depends on 24) A liquid crystal display device comprising the liquid crystal display unit according to claim 24 and a light source device. ### Claim 26 (depends on 19) A liquid crystal display device comprising the active matrix substrate according to claim 19, wherein signal potentials of a same polarity are supplied to respective data signal lines during one vertical period. ### Claim 27 (depends on 25) A television receiver comprising the liquid crystal display device according to claim 25 and a tuner section that receives a television broadcasting.