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US 8,570,414 B2Granted
Multiplexed read-out architecture for CMOS image sensors
AssigneeTexas Instruments Incorporated
InventorJose Tejada-Gomez
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Abstract
This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.
Claims6
A method of processing data from an electronic imager comprising the steps of:
- sampling a pixel offset level for a pixel of a predetermined row and storing a charge in a pixel offset column capacitor of a corresponding column of pixels;
- connecting said pixel offset column capacitor to an imager output during a first time interval including
- connecting said pixel offset column capacitor to a pixel offset bus shared among plural columns, and
- simultaneously connecting said pixel offset bus to an input of an output buffer;
- sampling a pixel signal level for said pixel of said predetermined row and storing a charge in a pixel signal column capacitor of said corresponding column of pixels;
- connecting said pixel signal column capacitor to said imager output during a second time interval distinct from said first time interval including
- connecting said pixel signal column capacitor to a pixel signal bus shared among plural columns, and
- simultaneously connecting said pixel signal bus to said input of said output buffer;
- and
- subtracting said pixel offset level from said pixel signal level for said pixel employing a correlated double sampler circuit.
7 more elements
A method of processing data from an electronic imager comprising the steps of:
- sampling a pixel offset level for a pixel of a predetermined row and storing a charge in a pixel offset column capacitor of a corresponding column of pixels;
- connecting said pixel offset column capacitor to an imager output during said first time interval including
- connecting said pixel offset column capacitor to an input of a column buffer for said column, and
- simultaneously connecting an output of said column buffer to an input of an output buffer;
- sampling a pixel signal level for said pixel of said predetermined row and storing a charge in a pixel signal column capacitor of said corresponding column of pixels;
- connecting said pixel signal column capacitor to said imager output during a second time interval distinct from said first time interval including
- connecting said pixel signal column capacitor to said input of said column buffer for said column, and
- simultaneously connecting an output of said column buffer to said input of said output buffer;
- and
- subtracting said pixel offset level from said pixel signal level for said pixel employing a correlated double sampler circuit.
7 more elements
Dependencies are inferred from the claim text.