# US 8,570,333 B2 · Method and system for enabling managed code-based application program to access graphics processing unit

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- Number: US 8,570,333 B2
- Document ID: US8570333B2
- Status: Granted
- Kind: B2
- Application number: 12/333,217
- Filed: 2008-12-11
- Published: 2010-06-17
- Granted: 2013-10-29
- Earliest claimed: 2008-12-11
- Assignees: NVIDIA Corporation
- Applicants: Meng-Shiue Yu
- Inventors: Meng-Shiue Yu
- Web page: https://patentgrep.com/patent/US8570333B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 8/45: {Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions}
- G06F 9/45516: {Runtime code conversion or optimisation}
- G06T 15/005: {General purpose rendering architectures}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

One embodiment of the present invention sets forth a method for enabling an intermediate code-based application program to access a target graphics processing unit (GPU) in a parallel processing environment. The method includes the steps of compiling a source code of the intermediate code-based application program to an intermediate code, translating the intermediate code to a PTX instruction code, and translating the PTX instruction code to a machine code executable by the target graphics processing unit before delivering the machine code to the target GPU.

## Claims

### Claim 1

A method for enabling an intermediate code-based application program to access a target graphics processing unit (GPU) in a parallel processing environment, comprising:
compiling a source code of the intermediate code-based application program to an intermediate code;
translating the intermediate code to a PTX instruction code; and
translating the PTX instruction code to a machine code executable by the target GPU before delivering the machine code to the target GPU;
wherein the intermediate code is a managed code that is configured to be executed under the management of a first virtual machine, and
wherein the first virtual machine comprises a first virtual clustering service associated with a host computer configured to query availability of the target GPU by communicating with a second virtual clustering service associated with the target GPU.

### Claim 2 (depends on 1)

The method of claim 1, further comprising preparing the first virtual machine in the host computer that is in a communication with a first graphics system and a second virtual machine in the first graphics system having the target GPU.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
encapsulating a set of selectable functions into an object; and
delivering the object and the PTX instruction code to the first graphics system.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first graphics system further stores a first application processing interface (API) that is supportive of the set of selectable functions encapsulated in the object.

### Claim 5 (depends on 2)

The method of claim 2, wherein translating the PTX instruction code to the machine code is performed in the first graphics system.

### Claim 6 (depends on 2)

The method of claim 2, further comprising determining an availability of the target GPU by establishing communication between the first virtual machine and the second virtual machine.

### Claim 7 (depends on 6)

The method of claim 6, wherein at the time of accessing the target GPU in a second graphics system of the host computer, translating the PTX instruction code to the machine code in the host computer.

### Claim 8

A parallel processing-capable computer system for enabling an intermediate code-based application program to access a target graphics processing unit (GPU), comprising:
a first graphics system with the target GPU;
a device memory comprising a first virtual machine; and
a host computer that is in communication with the first graphics system, comprising:
a second virtual machine; and
a system memory wherein the system memory comprises:
a compiler for compiling a source code of the intermediate code-based application program to an intermediate code;
a translator for translating the intermediate code to a PTX instruction code; and
a first application programming interface (API);
wherein the intermediate code is a managed code that is configured to be executed under the management of the second virtual machine, and
wherein the first virtual machine comprises a first virtual clustering service and the second virtual machine comprises a second virtual clustering service, and,
wherein the second virtual clustering service is configured to query the availability of the target GPU by communicating with the first virtual clustering service.

### Claim 9 (depends on 8)

The computer system of claim 8, wherein the system memory further comprises a parallel computing class for encapsulating a set of selectable functions into an object, and delivering the object and the PTX instruction code to the first graphics system.

### Claim 10 (depends on 9)

The computer system of claim 9, wherein the device memory of the first graphics system further stores a second API that is supportive of the set of selectable functions encapsulated in the object.

### Claim 11 (depends on 10)

The computer system of claim 10, wherein the second API is further utilized for translating the PTX instruction code to the machine code.

### Claim 12 (depends on 9)

The computer system of claim 9, wherein the second virtual machine determines an availability of the target GPU by establishing communication with the first virtual machine.

### Claim 13 (depends on 12)

The computer system of claim 12, wherein at the time of accessing the target GPU in a second graphics system of the host computer, the first API is utilized to translate the PTX instruction code to the machine code.

### Claim 14

A non-transitory computer-readable medium containing a sequence of instructions executable within a computer system including a host computer having a processing unit and a physical memory, wherein the sequence of instructions, when executed by the processing unit, causes the processing unit to:
compile a source code of an intermediate code-based application program to an intermediate code;
translate the intermediate code to a PTX instruction code; and
translate the PTX instruction code to a machine code that is executable by the target GPU before delivering the machine code to the target GPU;
wherein the intermediate code is a managed code that is configured to be executed under the management of a first virtual machine, and
wherein the first virtual machine comprises a first virtual clustering service associated with the host computer configured to query availability of the target GPU by communicating with a second virtual clustering service associated with the target GPU.

### Claim 15 (depends on 14)

The computer-readable medium of claim 14, further comprising a sequence of instructions when executed by the processing unit causes the processing unit to create the first virtual machine in the host computer and a second virtual machine in a first graphics system with a target graphics processing unit (GPU).

### Claim 16 (depends on 15)

The computer-readable medium of claim 15, further comprising a sequence of instructions when executed by the first virtual machine causes the first virtual machine to encapsulate a selectable predetermined set of functions into an object, and deliver the object and the PTX instruction code to the first graphics system.

### Claim 17 (depends on 15)

The computer-readable medium of claim 15, further comprising a sequence of instructions when executed by the processing unit causes the processing unit to enable the first virtual machine to determine an availability of the target GPU by establishing a communication with the second virtual machine.

### Claim 18 (depends on 14)

The computer-readable medium of claim 14, further comprising a sequence of instructions when executed by the processing unit causes the processing unit to enable an application programming interface (API) to translate the PTX instruction code to the corresponding machine code.