# US 8,570,332 B2 · Graphics processing system with power-gating control function, power-gating control method, and computer program products thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,332 B2 - Document ID: US8570332B2 - Status: Granted - Kind: B2 - Application number: 12/569,701 - Filed: 2009-09-29 - Published: 2010-11-25 - Granted: 2013-10-29 - Earliest claimed: 2009-05-25 - Assignees: Institute for Information Industry - Applicants: Chia-Lin Yang; Po-Han Wang; Yu-Jung Cheng - Inventors: Chia-Lin Yang; Po-Han Wang; Yu-Jung Cheng - Web page: https://patentgrep.com/patent/US8570332B2 ## CPC - G06T 15/005: {General purpose rendering architectures} - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands - G06F 1/3243: {Power saving in microcontroller unit} - G06T 2200/28: involving image processing hardware - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders. ## Claims ### Claim 1 A power-gating control method for a graphics processing unit having a unified shader unit, which comprises a plurality of shaders, comprising: rendering a plurality of previous frames via first active shaders of the plurality of shaders; calculating a number of the first active shaders required for rendering each of the plurality of previous frames, and respective frame rate of each of the plurality of previous frames; determining a number of second active shaders of the plurality of shaders used for rendering a next frame immediately following the previous frames based on the calculated number of the first active shaders required for rendering each of the plurality of previous frame and the calculated frame rate of each previous frame; and activating corresponding shaders of the plurality of shaders through one or more power-gating control elements according to the determined number of the second active shaders used for rendering the next frame immediately following the previous frames. ### Claim 2 (depends on 1) The power-gating control method as claimed in claim 1, further comprising: rendering the next frame by use of the activated shaders. ### Claim 3 (depends on 1) The power-gating control method as claimed in claim 1, further comprising: executing a first application program; and calculating the first number of active shaders and the corresponding frame rate of each previous frame in response to the execution of the first application program, wherein the first application program corresponds to the end of each previous frame. ### Claim 4 (depends on 1) The power-gating control method as claimed in claim 1, wherein determining the second number of active shaders comprises: obtaining a power state of each shader prior to determining the second number of active shaders. ### Claim 5 (depends on 4) The power-gating control method as claimed in claim 4, wherein activating the corresponding shaders comprises: executing a second application program; and generating a command packet in response to the execution of the second application program according to the second number of active shaders and the power state of each shader, for controlling the one or more power-gating control elements, wherein the second application program corresponds to the start of the next frame. ### Claim 6 (depends on 5) The power-gating control method as claimed in claim 5, further comprising: generating one or more control signals in response to the command packet, wherein each power-gating control element is turned on or turned off by a corresponding control signal. ### Claim 7 (depends on 6) The power-gating control method as claimed in claim 6, wherein each power-gating control element comprises a transistor coupled between a voltage source and at least one shader, and the transistor determines whether the at least one shader is supplied by the voltage source according to the corresponding control signal. ### Claim 8 (depends on 1) The power-gating control method as claimed in claim 1, wherein the shaders comprise a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto. ### Claim 9 (depends on 1) The power-gating control method as claimed in claim 1, wherein the second number of active shaders is generated by the following formula: S n + 1 = ⌈ Target_FPS + α min ⁢ { FPS n S n , FPS n - 1 S n - 1 , Λ , FPS n - m + 1 S n - m + 1 } ⌉ , wherein Sn+1 represents the second number of active shaders for rendering the next frame, M represents the number of the previous frames, Sn,Sn−1, . . . ,Sn−m+1 represents the first number of active shaders for rendering each previous frame, FPSn,FPSn−1, . . . ,FPSn−m+1 represents the frame rate corresponding to each previous frame, Target _FPS represents a target frame rate, α represents a control variable, and n≧m. ### Claim 10 A graphics processing system with power-gating control function comprising: a graphics processing unit, comprising a unified shader unit and one or more power-gating control elements, the unified shade comprising a plurality of shaders, wherein the plurality of shaders comprises first active shaders for rendering a plurality of previous frames and the one or more power-gating control elements are coupled to the shaders; and a driver coupled to the graphics processing unit for calculating a number of the first active shaders required for rendering each of the plurality of previous frames and respective frame rate of each of the plurality of previous frames, and determining a number of second active shaders of the plurality of shaders used for rendering a next frame immediately following the previous frames based on the calculated number of the first active shaders required for rendering each of the plurality of previous frame and the calculated frame rate of each previous frame, wherein the one or more power-gating control elements are configured to activate corresponding shaders of the plurality of shaders according to the determined number of the second active shaders used for rendering the next frame immediately following the previous frames. ### Claim 11 (depends on 10) The graphics processing system as claimed in claim 10, wherein the graphics processing system renders the next frame by use of the activated shaders. ### Claim 12 (depends on 10) The graphics processing system as claimed in claim 10, wherein when a first application program is executed, in response to the execution of the first application program, the driver calculates the first number of active shaders and the corresponding frame rate of each previous frame, and the first application program corresponds to the end of each previous frame. ### Claim 13 (depends on 10) The graphics processing system as claimed in claim 10, wherein the driver obtains a power state of each shader prior to determining the second number of active shaders. ### Claim 14 (depends on 13) The graphics processing system as claimed in claim 13, wherein when a second application program is executed, in response to the execution of the second application program, the driver generates a command packet according the second number of active shaders and the power state of each shader, for controlling the one or more power-gating control elements, and the second application program corresponds to the start of the next frame. ### Claim 15 (depends on 14) The graphics processing system as claimed in claim 14, wherein the graphics processing unit comprises: a command processor coupled to the driver for generating one or more control signals in response to the command packet, wherein each power-gating control element is turned on or turned off by a corresponding control signal. ### Claim 16 (depends on 15) The graphics processing system as claimed in claim 15, wherein each power-gating control element comprises a transistor coupled between a voltage source and at least one shader the transistor determines whether the at least one shader is supplied by the voltage source according to the corresponding control signal. ### Claim 17 (depends on 10) The graphics processing system as claimed in claim 10, wherein the shaders comprises a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto. ### Claim 18 (depends on 10) The graphics processing system as claimed in claim 10, wherein the second number of active shaders is generated by the following formula: S n + 1 = ⌈ Target_FPS + α min ⁢ { FPS n S n , FPS n - 1 S n - 1 , Λ , FPS n - m + 1 S n - m + 1 } ⌉ , wherein Sn+1 represents the second number of active shaders for rendering the next frame, M represents the number of the previous frames, Sn,Sn−1, . . . , Sn−m+1 represents the first number of active shaders for rendering each previous frame, FPSn, FPSn−1, . . . , FPSn−m+1 represents the frame rate corresponding to each previous frame, Target _FPS represents a target frame rate, α represents a control variable, and n ≧m. ### Claim 19 A computer program product comprising a non-transitory computer-readable storage medium having computer-executable program code instructions stored therein, the computer program product being loaded into and executed by a machine to perfoun a power-gating control method for a graphics processing unit having a unified shader unit, which comprises a plurality of shaders, the computer-executable program code instructions comprising: a first program code for rendering a plurality of previous frames via first active shaders of the plurality of shaders; a second program code for calculating a number of the first active shaders required for rendering each of the plurality of previous frames, and respective frame rate of each of the plurality of previous frames; a third program code for determining a number of second active shaders of the plurality of shaders used for rendering a next frame immediately following the previous frames based on the calculated number of the first active shaders required for rendering each of the plurality of previous frame and the calculated frame rate of each previous frame; and a fourth program code for activating corresponding shaders of the plurality of shaders through one or more power-gating control elements according to the determined number of the second active shaders used for rendering the next frame immediately following the previous frames. ### Claim 20 (depends on 19) The computer program product as claimed in claim 19, wherein the shaders comprise a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto. ### Claim 21 (depends on 19) The computer program product as claimed in claim 19, wherein the second number of active shaders is generated by the following formula: S n + 1 = ⌈ Target_FPS + α min ⁢ { FPS n S n , FPS n - 1 S n - 1 , Λ , FPS n - m + 1 S n - m + 1 } ⌉ , wherein Sn+1 represents the second number of active shaders for rendering the next frame, m represents the number of the previous frames, Sn , Sn−1, . . . ., Sn−m+1 represents the first number of active shaders for rendering each previous frame, FPSn,FPSn−1, . . . , FPSn−m+1 represents the frame rate corresponding to each previous frame, Target _FPS represents a target frame rate, α represents a control variable, and n ≧m.