# US 8,570,309 B2 · Buffer and organic light emitting display using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,309 B2 - Document ID: US8570309B2 - Status: Granted - Kind: B2 - Application number: 12/418,293 - Filed: 2009-04-03 - Published: 2009-10-29 - Granted: 2013-10-29 - Earliest claimed: 2008-04-25 - Assignees: Samsung Display Co., Ltd. - Applicants: Jin-Tae Jeong - Inventors: Jin-Tae Jeong - Web page: https://patentgrep.com/patent/US8570309B2 ## CPC - G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED] - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A buffer and an organic light emitting display using the same that reduces (or prevents) a signal of the organic light emitting display from being delayed by improving an output signal of the buffer. The buffer includes an input unit between a first power source and a second power source having a voltage lower than the first power source, and for receiving an input signal to output a first signal; a first inverter between the first and second power sources, and for receiving the first signal and the input signal to output a second signal obtained by inverting the first signal; a second inverter between the first and second power sources, and for receiving the second signal and the first signal to output a third signal obtained by inverting the second signal; and an output unit coupled between the first power source and a third power source having a voltage lower than the second power source, and for receiving the third signal and the second signal to output an output signal obtained by inverting the third signal. ## Claims ### Claim 1 A buffer comprising: an input unit between a first power source and a second power source having a voltage lower than the first power source, and for receiving an input signal to output a first signal; a first inverter between the first and second power sources, and for receiving the first signal and the input signal to output a second signal obtained by inverting the first signal; a second inverter between the first and second power sources, and for receiving the second signal and the first signal to output a third signal obtained by inverting the second signal; and an output unit coupled between the first power source and a third power source having a voltage lower than the second power source, and for receiving the third signal and the second signal to output an output signal obtained by inverting the third signal, wherein the input unit comprises first, second and third transistors coupled in series between the first and second power sources, the third transistor comprising a gate directly electrically connected to the second power source. ### Claim 2 (depends on 1) The buffer as claimed in claim 1, wherein: the first transistor comprises a source coupled to the first power source, a drain coupled to a first node, and a gate coupled to an input terminal for receiving the input signal; the second transistor comprises a source coupled to the first node, a drain coupled to a source of the third transistor, and a gate coupled to the second power source; and the third transistor comprises the source coupled to the drain of the second transistor and a drain coupled to the second power source. ### Claim 3 (depends on 2) The buffer as claimed in claim 2, wherein the first inverter comprises: a fourth transistor including a source coupled to the first power source, a drain coupled to a second node, and a gate for receiving the first signal; and a fifth transistor including a source coupled to the second node, a drain coupled to the second power source, and a gate for receiving the input signal. ### Claim 4 (depends on 3) The buffer as claimed in claim 3, wherein the second inverter comprises: a sixth transistor including a source coupled to the first power source, a drain coupled to a third node, and a gate for receiving the second signal; and a seventh transistor including a source coupled to the third node, a drain coupled to the second power source, and a gate for receiving the first signal. ### Claim 5 (depends on 4) The buffer as claimed in claim 4, wherein the output unit comprises: an eighth transistor including a source coupled to the first power source, a drain coupled to an output terminal for outputting the output signal, and a gate for receiving the third signal; and a ninth transistor including a source coupled to the output terminal, a drain coupled to the third power source, and a gate for receiving the second signal. ### Claim 6 (depends on 5) The buffer as claimed in claim 5, further comprising a capacitor coupled between the output terminal and the gate of the ninth transistor. ### Claim 7 (depends on 1) The buffer as claimed in claim 1, wherein the first inverter comprises: a first transistor including a source coupled to the first power source, a drain coupled to a node, and a gate for receiving the first signal; and a second transistor including a source coupled to the node, a drain coupled to the second power source, and a gate for receiving the input signal. ### Claim 8 (depends on 1) The buffer as claimed in claim 1, wherein the second inverter comprises: a first transistor including a source coupled to the first power source, a drain coupled to a node, and a gate for receiving the second signal; and a second transistor including a source coupled to the node, a drain coupled to the second power source, and a gate for receiving the first signal. ### Claim 9 (depends on 1) The buffer as claimed in claim 1, wherein the output unit comprises: a first transistor including a source coupled to the first power source, a drain coupled to an output terminal for outputting the output signal, and a gate for receiving the third signal; and a second transistor including a source coupled to the output terminal, a drain coupled to the third power source, and a gate for receiving the second signal. ### Claim 10 (depends on 9) The buffer as claimed in claim 9, further comprising a capacitor coupled between the output terminal and the gate of the second transistor. ### Claim 11 An organic light emitting display, comprising: a pixel unit having a plurality of pixels arranged therein; and a buffer for amplifying and providing a test signal to the pixel unit to test the pixel unit, the buffer comprising: an input unit between a first power source and a second power source having a voltage lower than the first power source, and for receiving an input signal to output a first signal; a first inverter between the first and second power sources, and for receiving the first signal and the input signal to output a second signal obtained by inverting the first signal; a second inverter between the first and second power sources, and for receiving the second signal and the first signal to output a third signal obtained by inverting the second signal; and an output unit coupled between the first power source and a third power source having a voltage lower than the second power source, and for receiving the third signal and the second signal to output an output signal obtained by inverting the third signal, wherein the input unit comprises first, second and third transistors coupled in series between the first and second power sources, the third transistor comprising a gate directly electrically connected to the second power source. ### Claim 12 (depends on 11) The organic light emitting display as claimed in claim 11, wherein: the first transistor comprises a source coupled to the first power source, a drain coupled to a first node, and a gate coupled to an input terminal for receiving the input signal; the second transistor comprises a source coupled to the first node, a drain coupled to a source of the third transistor, and a gate coupled to the second power source; and the third transistor comprises the source coupled to the drain of the second transistor and a drain coupled to the second power source. ### Claim 13 (depends on 12) The organic light emitting display as claimed in claim 12, wherein the first inverter comprises: a fourth transistor including a source coupled to the first power source, a drain coupled to a second node, and a gate for receiving the first signal; and a fifth transistor including a source coupled to the second node, a drain coupled to the second power source, and a gate for receiving the input signal. ### Claim 14 (depends on 13) The organic light emitting display as claimed in claim 13, wherein the second inverter comprises: a sixth transistor including a source coupled to the first power source, a drain coupled to a third node, and a gate for receiving the second signal; and a seventh transistor including a source coupled to the third node, a drain coupled to the second power source, and a gate for receiving the first signal. ### Claim 15 (depends on 14) The organic light emitting display as claimed in claim 14, wherein the output unit comprises: an eighth transistor including a source coupled to the first power source, a drain coupled to an output terminal for outputting the output signal, and a gate for receiving the third signal; and a ninth transistor including a source coupled to the output terminal, a drain coupled to the third power source, and a gate for receiving the second signal. ### Claim 16 (depends on 15) The organic light emitting display as claimed in claim 15, further comprising a capacitor coupled between the output terminal and the gate of the ninth transistor. ### Claim 17 (depends on 11) The organic light emitting display as claimed in claim 11, wherein the first inverter comprises: a first transistor including a source coupled to the first power source, a drain coupled to a node, and a gate for receiving the first signal; and a second transistor including a source coupled to the node, a drain coupled to the second power source, and a gate for receiving the input signal. ### Claim 18 (depends on 11) The organic light emitting display as claimed in claim 11, wherein the second inverter comprises: a first transistor including a source coupled to the first power source, a drain coupled to a node, and a gate for receiving the second signal; and a second transistor including a source coupled to the node, a drain coupled to the second power source, and a gate for receiving the first signal. ### Claim 19 (depends on 11) The organic light emitting display as claimed in claim 11, wherein the output unit comprises: a first transistor including a source coupled to the first power source, a drain coupled to an output terminal for outputting the output signal, and. a gate for receiving the third signal; and a second transistor including a source coupled to the output terminal, a drain coupled to the third power source, and a gate for receiving the second signal. ### Claim 20 (depends on 19) The organic light emitting display as claimed in claim 19, further comprising a capacitor coupled between the output terminal and the gate of the second transistor.